Simulation Results: aes/masked

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.37 %
  • code
  • 98.14 %
  • assert
  • 98.57 %
  • func
  • 95.41 %
  • block
  • 98.22 %
  • line
  • 99.38 %
  • branch
  • 95.04 %
  • toggle
  • 98.13 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.85%
V2S
97.82%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 131.876us 1 1 100.00
smoke 50 50 100.00
aes_smoke 5.000s 95.586us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 3.000s 90.322us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 2.000s 69.467us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 11.000s 9345.181us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 3.000s 231.296us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 377.662us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 2.000s 69.467us 20 20 100.00
aes_csr_aliasing 3.000s 231.296us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 5.000s 95.586us 50 50 100.00
aes_config_error 6.000s 88.610us 50 50 100.00
aes_stress 20.000s 713.963us 50 50 100.00
key_length 150 150 100.00
aes_smoke 5.000s 95.586us 50 50 100.00
aes_config_error 6.000s 88.610us 50 50 100.00
aes_stress 20.000s 713.963us 50 50 100.00
back2back 100 100 100.00
aes_stress 20.000s 713.963us 50 50 100.00
aes_b2b 25.000s 364.284us 50 50 100.00
backpressure 50 50 100.00
aes_stress 20.000s 713.963us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 5.000s 95.586us 50 50 100.00
aes_config_error 6.000s 88.610us 50 50 100.00
aes_stress 20.000s 713.963us 50 50 100.00
aes_alert_reset 13.000s 1200.953us 50 50 100.00
failure_test 149 150 99.33
aes_man_cfg_err 4.000s 119.691us 49 50 98.00
aes_config_error 6.000s 88.610us 50 50 100.00
aes_alert_reset 13.000s 1200.953us 50 50 100.00
trigger_clear_test 50 50 100.00
aes_clear 16.000s 726.714us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 282.642us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 12.000s 270.271us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 13.000s 1200.953us 50 50 100.00
stress 50 50 100.00
aes_stress 20.000s 713.963us 50 50 100.00
sideload 100 100 100.00
aes_stress 20.000s 713.963us 50 50 100.00
aes_sideload 16.000s 780.255us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 7.000s 127.250us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 164.000s 6103.942us 10 10 100.00
gcm_save_and_restore 100 100 100.00
aes_gcm_save_restore 19.000s 1110.991us 100 100 100.00
alert_test 50 50 100.00
aes_alert_test 3.000s 110.043us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 4.000s 314.884us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 4.000s 314.884us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 3.000s 90.322us 5 5 100.00
aes_csr_rw 2.000s 69.467us 20 20 100.00
aes_csr_aliasing 3.000s 231.296us 5 5 100.00
aes_same_csr_outstanding 3.000s 64.609us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 3.000s 90.322us 5 5 100.00
aes_csr_rw 2.000s 69.467us 20 20 100.00
aes_csr_aliasing 3.000s 231.296us 5 5 100.00
aes_same_csr_outstanding 3.000s 64.609us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 105.000s 4182.391us 50 50 100.00
fault_inject 669 700 95.57
aes_fi 24.000s 1326.945us 50 50 100.00
aes_control_fi 59.000s 10004.744us 283 300 94.33
aes_cipher_fi 51.000s 10011.230us 336 350 96.00
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 233.899us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 233.899us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 233.899us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 233.899us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 436.190us 20 20 100.00
tl_intg_err 25 25 100.00
aes_tl_intg_err 4.000s 1082.172us 20 20 100.00
aes_sec_cm 8.000s 1893.812us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 4.000s 1082.172us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 13.000s 1200.953us 50 50 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 233.899us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 233.899us 20 20 100.00
sec_cm_main_config_sparse 220 220 100.00
aes_smoke 5.000s 95.586us 50 50 100.00
aes_stress 20.000s 713.963us 50 50 100.00
aes_alert_reset 13.000s 1200.953us 50 50 100.00
aes_core_fi 11.000s 499.435us 70 70 100.00
sec_cm_gcm_config_sparse 270 270 100.00
aes_gcm_save_restore 19.000s 1110.991us 100 100 100.00
aes_config_error 6.000s 88.610us 50 50 100.00
aes_stress 20.000s 713.963us 50 50 100.00
aes_core_fi 11.000s 499.435us 70 70 100.00
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 233.899us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 4.000s 96.960us 50 50 100.00
aes_stress 20.000s 713.963us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 20.000s 713.963us 50 50 100.00
aes_sideload 16.000s 780.255us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 4.000s 96.960us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 4.000s 96.960us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 4.000s 96.960us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 4.000s 96.960us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 4.000s 96.960us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 20.000s 713.963us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 20.000s 713.963us 50 50 100.00
sec_cm_main_fsm_sparse 50 50 100.00
aes_fi 24.000s 1326.945us 50 50 100.00
sec_cm_main_fsm_redun 719 750 95.87
aes_fi 24.000s 1326.945us 50 50 100.00
aes_control_fi 59.000s 10004.744us 283 300 94.33
aes_cipher_fi 51.000s 10011.230us 336 350 96.00
aes_ctr_fi 3.000s 77.724us 50 50 100.00
sec_cm_cipher_fsm_sparse 50 50 100.00
aes_fi 24.000s 1326.945us 50 50 100.00
sec_cm_cipher_fsm_redun 669 700 95.57
aes_fi 24.000s 1326.945us 50 50 100.00
aes_control_fi 59.000s 10004.744us 283 300 94.33
aes_cipher_fi 51.000s 10011.230us 336 350 96.00
sec_cm_cipher_ctr_redun 336 350 96.00
aes_cipher_fi 51.000s 10011.230us 336 350 96.00
sec_cm_ctr_fsm_sparse 50 50 100.00
aes_fi 24.000s 1326.945us 50 50 100.00
sec_cm_ctr_fsm_redun 383 400 95.75
aes_fi 24.000s 1326.945us 50 50 100.00
aes_control_fi 59.000s 10004.744us 283 300 94.33
aes_ctr_fi 3.000s 77.724us 50 50 100.00
sec_cm_ghash_fsm_sparse 50 50 100.00
aes_fi 24.000s 1326.945us 50 50 100.00
sec_cm_ctrl_sparse 719 750 95.87
aes_fi 24.000s 1326.945us 50 50 100.00
aes_control_fi 59.000s 10004.744us 283 300 94.33
aes_cipher_fi 51.000s 10011.230us 336 350 96.00
aes_ctr_fi 3.000s 77.724us 50 50 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 13.000s 1200.953us 50 50 100.00
sec_cm_main_fsm_local_esc 719 750 95.87
aes_fi 24.000s 1326.945us 50 50 100.00
aes_control_fi 59.000s 10004.744us 283 300 94.33
aes_cipher_fi 51.000s 10011.230us 336 350 96.00
aes_ctr_fi 3.000s 77.724us 50 50 100.00
sec_cm_cipher_fsm_local_esc 719 750 95.87
aes_fi 24.000s 1326.945us 50 50 100.00
aes_control_fi 59.000s 10004.744us 283 300 94.33
aes_cipher_fi 51.000s 10011.230us 336 350 96.00
aes_ctr_fi 3.000s 77.724us 50 50 100.00
sec_cm_ctr_fsm_local_esc 383 400 95.75
aes_fi 24.000s 1326.945us 50 50 100.00
aes_control_fi 59.000s 10004.744us 283 300 94.33
aes_ctr_fi 3.000s 77.724us 50 50 100.00
sec_cm_ghash_fsm_local_esc 140 140 100.00
aes_fi 24.000s 1326.945us 50 50 100.00
aes_ghash_fi 9.000s 449.925us 90 90 100.00
sec_cm_data_reg_local_esc 669 700 95.57
aes_fi 24.000s 1326.945us 50 50 100.00
aes_control_fi 59.000s 10004.744us 283 300 94.33
aes_cipher_fi 51.000s 10011.230us 336 350 96.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 43.000s 6637.809us 0 10 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes
aes_cipher_fi 61556026805574783893879986112808399072067483715271867306438295495170726234188 None
Job timed out after 1 minutes
aes_control_fi 34994065989661244330277603100839885243019603136477519510190288918152056621950 None
Job timed out after 1 minutes
aes_cipher_fi 2280703292085106774863302495458704880602701036007680244651069476533015751958 None
Job timed out after 1 minutes
aes_control_fi 111519982492428878468322060303546696867041987060952377502887074052736628874608 None
Job timed out after 1 minutes
aes_cipher_fi 104118742155107850569564046843026008535111707776430669528511539745911432138945 None
Job timed out after 1 minutes
aes_cipher_fi 47049338669968320294676926544339381316885934942190908253156170296719281703428 None
Job timed out after 1 minutes
aes_control_fi 37984542675833372065758708338128490802031199303466703375567100979792054205928 None
Job timed out after 1 minutes
aes_control_fi 58348607464250512264520268900370076541425343722912877791774771966681557795586 None
Job timed out after 1 minutes
aes_control_fi 108632726405509898778977155321595636787722460132415623891057648972975114782256 None
Job timed out after 1 minutes
aes_control_fi 55049485782245542902790870126196129764202298921991451933814898557151366348130 None
Job timed out after 1 minutes
aes_control_fi 7136661886989427974781243579128680995459575468609347167335591524154116716852 None
Job timed out after 1 minutes
aes_control_fi 9771381387874151620220659226989819152310444976224657138395894843216217377322 None
Job timed out after 1 minutes
aes_cipher_fi 70191459128917993851265982528955007541434168386895712740446607742084205245065 None
Job timed out after 1 minutes
aes_control_fi 27266149458102693432998662017742866960679999528376305874514213623422468627794 None
Job timed out after 1 minutes
aes_cipher_fi 72596694293878958770802645556440685799674963449643343215256721344865927315332 None
Job timed out after 1 minutes
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 51354670745048710226379781061149853217639668960210919593413121705175310829182 448
UVM_ERROR @ 308523621 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 308523621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 40151647839361844673658195005643665779373720487043952909364902453603017064451 201
UVM_ERROR @ 55764572 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 55764572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 38863634559881733278649231423911094190535654524922671118210476086491241895931 200
UVM_ERROR @ 20625057 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 20625057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 101696754466633756619914777103632957983165597732459010793885496627063652377900 446
UVM_ERROR @ 910454784 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 910454784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 80883907373710497628439727424210865017614639745899900710553560807036896610608 620
UVM_ERROR @ 1605931032 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1605931032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 36393147676393797036453796538626889269890811839508013030186098305768832873959 235
UVM_ERROR @ 1266694521 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1266694521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:306) virtual_sequencer [aes_stress_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG
aes_stress_all_with_rand_reset 99334243689281759576495440312930936638918922348561802172437156299994141067410 464
UVM_FATAL @ 6637809280 ps: (aes_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG
UVM_INFO @ 6637809280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 2870379620134328038922120050838863828660452442603968379760468398343822673151 330
UVM_FATAL @ 1108979085 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 1108979085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:306) virtual_sequencer [aes_stress_vseq] Expected GCM phase GCM_AAD, got GCM_INIT
aes_stress_all_with_rand_reset 67425429021899119568716743618016580196176825311958308261449788440061399959108 243
UVM_FATAL @ 1570799031 ps: (aes_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Expected GCM phase GCM_AAD, got GCM_INIT
UVM_INFO @ 1570799031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 93821197606089017420438159587640511973050977803294228195569704026915930924571 791
UVM_FATAL @ 1026285776 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 1026285776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
aes_control_fi 38193014112058259021194269760810858442379503657809895749865399355195911186057 151
UVM_FATAL @ 10018057044 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10018057044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 91264329080149961867691347299227502412111440408252489400192243124431158258553 144
UVM_FATAL @ 10004743924 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10004743924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 103084567731568051261469066702617775486923549652333203683440434764680475217922 155
UVM_FATAL @ 10098566286 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10098566286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 93753479300481088567893880746747874958659728097981419751925949578017766881088 155
UVM_FATAL @ 10013177680 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10013177680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 66578312356225674274264336763714109106214219885698255058676671501976226625509 145
UVM_FATAL @ 10009953045 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10009953045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 40905876555084327199645896970333694439833626461340992018541912184482576862616 153
UVM_FATAL @ 10012283728 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10012283728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 80946423359324697515654952551727278594221883160976259652835913762498315678249 147
UVM_FATAL @ 10036368290 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10036368290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 13267198147599789587182421439212559387417580389807446847649464984033030601931 140
UVM_FATAL @ 10029443661 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10029443661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_manual_config_err_vseq.sv:71) virtual_sequencer [aes_manual_config_err_vseq] WAS ABLE TO TRIGGER OPERATION WITH ILLEGAL MODE
aes_man_cfg_err 3668259697787141845101397409174450855041751442796810063448579718630738137370 141
UVM_FATAL @ 15160047 ps: (aes_manual_config_err_vseq.sv:71) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_manual_config_err_vseq] WAS ABLE TO TRIGGER OPERATION WITH ILLEGAL MODE
UVM_INFO @ 15160047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 62795600533015173101055787248139028317657269899437265981615926495017696742628 148
UVM_FATAL @ 10010423689 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10010423689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 81523739083666239009452491056055388415666344216808812915812091887766421675281 154
UVM_FATAL @ 10240826122 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10240826122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 38547205203021005935898364041084475424879678964903229731328216163476295587285 149
UVM_FATAL @ 10010745580 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10010745580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 108915805125835301289125402968626087630481392284687737123359788902644388288792 157
UVM_FATAL @ 10013429696 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10013429696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 71212397276281906154103459030196097862028084536681429555361118590314369573077 154
UVM_FATAL @ 10011230273 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10011230273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 13421535605112624126405718767699096867609356202748729142927728708059880670754 153
UVM_FATAL @ 10007073418 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007073418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 88386344892235681048024197790849010031797437598993485067458543015113852054509 143
UVM_FATAL @ 10009485186 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10009485186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 102830592430409215083170844908725188690218400220172546271166170751296856163142 143
UVM_FATAL @ 10022724985 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10022724985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---