Simulation Results: hmac

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.86 %
  • code
  • 99.23 %
  • assert
  • 97.36 %
  • func
  • 100.00 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.74 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 11.080s 4239.340us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.190s 64.469us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.320s 67.333us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 12.960s 4349.477us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 6.940s 1308.302us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 831.260s 254671.514us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.320s 67.333us 20 20 100.00
hmac_csr_aliasing 6.940s 1308.302us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 63.890s 1436.509us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 88.960s 1673.657us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 250.860s 5720.801us 30 30 100.00
hmac_test_sha384_vectors 552.980s 60993.034us 75 75 100.00
hmac_test_sha512_vectors 552.360s 14733.993us 75 75 100.00
hmac_test_hmac256_vectors 15.090s 1329.264us 50 50 100.00
hmac_test_hmac384_vectors 16.010s 400.465us 60 60 100.00
hmac_test_hmac512_vectors 20.280s 444.207us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 32.780s 2398.917us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 978.210s 11880.579us 10 10 100.00
error 10 10 100.00
hmac_error 109.390s 79472.112us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 66.410s 31761.852us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 11.080s 4239.340us 10 10 100.00
hmac_long_msg 63.890s 1436.509us 10 10 100.00
hmac_back_pressure 88.960s 1673.657us 25 25 100.00
hmac_datapath_stress 978.210s 11880.579us 10 10 100.00
hmac_burst_wr 32.780s 2398.917us 50 50 100.00
hmac_stress_all 2196.720s 54850.737us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 11.080s 4239.340us 10 10 100.00
hmac_long_msg 63.890s 1436.509us 10 10 100.00
hmac_back_pressure 88.960s 1673.657us 25 25 100.00
hmac_datapath_stress 978.210s 11880.579us 10 10 100.00
hmac_wipe_secret 66.410s 31761.852us 10 10 100.00
hmac_test_sha256_vectors 250.860s 5720.801us 30 30 100.00
hmac_test_sha384_vectors 552.980s 60993.034us 75 75 100.00
hmac_test_sha512_vectors 552.360s 14733.993us 75 75 100.00
hmac_test_hmac256_vectors 15.090s 1329.264us 50 50 100.00
hmac_test_hmac384_vectors 16.010s 400.465us 60 60 100.00
hmac_test_hmac512_vectors 20.280s 444.207us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 11.080s 4239.340us 10 10 100.00
hmac_long_msg 63.890s 1436.509us 10 10 100.00
hmac_back_pressure 88.960s 1673.657us 25 25 100.00
hmac_datapath_stress 978.210s 11880.579us 10 10 100.00
hmac_burst_wr 32.780s 2398.917us 50 50 100.00
hmac_error 109.390s 79472.112us 10 10 100.00
hmac_wipe_secret 66.410s 31761.852us 10 10 100.00
hmac_test_sha256_vectors 250.860s 5720.801us 30 30 100.00
hmac_test_sha384_vectors 552.980s 60993.034us 75 75 100.00
hmac_test_sha512_vectors 552.360s 14733.993us 75 75 100.00
hmac_test_hmac256_vectors 15.090s 1329.264us 50 50 100.00
hmac_test_hmac384_vectors 16.010s 400.465us 60 60 100.00
hmac_test_hmac512_vectors 20.280s 444.207us 75 75 100.00
hmac_stress_all 2196.720s 54850.737us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2196.720s 54850.737us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.940s 26.708us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.980s 14.783us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 3.860s 207.950us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 3.860s 207.950us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.190s 64.469us 5 5 100.00
hmac_csr_rw 1.320s 67.333us 20 20 100.00
hmac_csr_aliasing 6.940s 1308.302us 5 5 100.00
hmac_same_csr_outstanding 2.590s 91.829us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.190s 64.469us 5 5 100.00
hmac_csr_rw 1.320s 67.333us 20 20 100.00
hmac_csr_aliasing 6.940s 1308.302us 5 5 100.00
hmac_same_csr_outstanding 2.590s 91.829us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.120s 319.512us 5 5 100.00
hmac_tl_intg_err 4.810s 1734.672us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.810s 1734.672us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 11.080s 4239.340us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.730s 472.300us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 423.160s 27158.164us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.860s 12.710us 1 1 100.00