Simulation Results: kmac/masked

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.68 %
  • code
  • 94.08 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.18 %
  • branch
  • 97.01 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 79.58 %
Validation stages
V1
100.00%
V2
99.87%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 85.780s 23682.673us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.390s 118.760us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.420s 108.748us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 14.210s 983.353us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 8.260s 651.575us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.910s 63.363us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.420s 108.748us 20 20 100.00
kmac_csr_aliasing 8.260s 651.575us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.080s 18.715us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.780s 66.001us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3495.340s 137570.261us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1481.160s 35795.670us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2278.800s 330353.512us 5 5 100.00
kmac_test_vectors_sha3_256 2086.320s 159936.466us 5 5 100.00
kmac_test_vectors_sha3_384 1846.090s 372211.669us 5 5 100.00
kmac_test_vectors_sha3_512 1178.150s 31536.222us 5 5 100.00
kmac_test_vectors_shake_128 2524.560s 104818.920us 5 5 100.00
kmac_test_vectors_shake_256 1947.000s 299988.790us 5 5 100.00
kmac_test_vectors_kmac 3.680s 469.985us 5 5 100.00
kmac_test_vectors_kmac_xof 4.010s 583.264us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 487.010s 15877.705us 50 50 100.00
app 50 50 100.00
kmac_app 470.510s 19009.782us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 367.030s 60578.828us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 432.880s 64101.291us 50 50 100.00
error 50 50 100.00
kmac_error 516.480s 22051.400us 50 50 100.00
key_error 49 50 98.00
kmac_key_error 16.420s 3463.824us 49 50 98.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.340s 572.167us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 42.860s 8306.954us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 36.380s 4407.900us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 65.470s 13597.760us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 37.150s 511.968us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 4232.290s 678806.281us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.190s 17.490us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.270s 35.596us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.810s 149.324us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.810s 149.324us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.390s 118.760us 5 5 100.00
kmac_csr_rw 1.420s 108.748us 20 20 100.00
kmac_csr_aliasing 8.260s 651.575us 5 5 100.00
kmac_same_csr_outstanding 2.910s 1017.749us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.390s 118.760us 5 5 100.00
kmac_csr_rw 1.420s 108.748us 20 20 100.00
kmac_csr_aliasing 8.260s 651.575us 5 5 100.00
kmac_same_csr_outstanding 2.910s 1017.749us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.390s 99.625us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.390s 99.625us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.390s 99.625us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.390s 99.625us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.000s 1157.941us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 5.240s 1310.581us 20 20 100.00
kmac_sec_cm 72.660s 16428.873us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.240s 1310.581us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 37.150s 511.968us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 85.780s 23682.673us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 487.010s 15877.705us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.390s 99.625us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 72.660s 16428.873us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 72.660s 16428.873us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 72.660s 16428.873us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 85.780s 23682.673us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 37.150s 511.968us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 72.660s 16428.873us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 366.030s 16784.433us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 85.780s 23682.673us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 321.770s 17115.982us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 2458264426086448960251312371802802895899564046467593814474183879211526079270 215
UVM_ERROR @ 3348297058 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 3348297058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 67737442753073630591570408573395469956259881567606589660524509627736341968082 383
UVM_ERROR @ 7106571014 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 7106571014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 39163637061460600595474025980644253307449126923065874406578949981006384279858 202
UVM_ERROR @ 1595228760 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 1595228760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: *
kmac_key_error 97850995909229002558047502342028354629470404922929242230319083079610668155486 77
UVM_ERROR @ 73829353 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
UVM_INFO @ 73829353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---