Simulation Results: lc_ctrl/volatile_unlock_disabled

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.78 %
  • code
  • 88.95 %
  • assert
  • 95.99 %
  • func
  • 96.40 %
  • line
  • 97.90 %
  • branch
  • 96.99 %
  • cond
  • 82.13 %
  • toggle
  • 91.35 %
  • FSM
  • 76.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
42.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 7.710s 581.845us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.400s 75.502us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.270s 51.263us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 3.170s 411.576us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.790s 59.297us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.760s 32.195us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.270s 51.263us 20 20 100.00
lc_ctrl_csr_aliasing 1.790s 59.297us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 8.910s 115.929us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.300s 951.423us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.290s 45.890us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 3.600s 344.412us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 15.910s 325.246us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 14.020s 487.312us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 15.910s 325.246us 50 50 100.00
lc_ctrl_prog_failure 3.600s 344.412us 50 50 100.00
lc_ctrl_errors 14.020s 487.312us 50 50 100.00
lc_ctrl_security_escalation 11.110s 1780.628us 50 50 100.00
lc_ctrl_jtag_state_failure 60.870s 5040.177us 20 20 100.00
lc_ctrl_jtag_prog_failure 23.510s 1184.358us 20 20 100.00
lc_ctrl_jtag_errors 102.760s 5067.237us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_csr_hw_reset 2.490s 237.736us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.080s 199.739us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 36.170s 8485.794us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 18.150s 4912.579us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.910s 291.366us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.400s 520.954us 10 10 100.00
lc_ctrl_jtag_alert_test 1.850s 547.050us 10 10 100.00
lc_ctrl_jtag_smoke 13.940s 1460.036us 20 20 100.00
lc_ctrl_jtag_state_post_trans 33.600s 2831.103us 20 20 100.00
lc_ctrl_jtag_prog_failure 23.510s 1184.358us 20 20 100.00
lc_ctrl_jtag_errors 102.760s 5067.237us 20 20 100.00
lc_ctrl_jtag_access 24.960s 1286.727us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 26.450s 1097.388us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 28.480s 6651.657us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.540s 31.242us 50 50 100.00
stress_all 50 50 100.00
lc_ctrl_stress_all 303.890s 19299.997us 50 50 100.00
alert_test 50 50 100.00
lc_ctrl_alert_test 2.110s 83.346us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.320s 244.910us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.320s 244.910us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.400s 75.502us 5 5 100.00
lc_ctrl_csr_rw 1.270s 51.263us 20 20 100.00
lc_ctrl_csr_aliasing 1.790s 59.297us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.880s 41.709us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.400s 75.502us 5 5 100.00
lc_ctrl_csr_rw 1.270s 51.263us 20 20 100.00
lc_ctrl_csr_aliasing 1.790s 59.297us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.880s 41.709us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 4.290s 492.253us 20 20 100.00
lc_ctrl_sec_cm 9.110s 244.912us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.290s 492.253us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.300s 951.423us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 15.910s 325.246us 50 50 100.00
lc_ctrl_sec_cm 9.110s 244.912us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 15.910s 325.246us 50 50 100.00
lc_ctrl_sec_cm 9.110s 244.912us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 15.910s 325.246us 50 50 100.00
lc_ctrl_sec_cm 9.110s 244.912us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 15.910s 325.246us 50 50 100.00
lc_ctrl_sec_cm 9.110s 244.912us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 15.910s 325.246us 50 50 100.00
lc_ctrl_sec_cm 9.110s 244.912us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 15.910s 325.246us 50 50 100.00
lc_ctrl_sec_cm 9.110s 244.912us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 15.910s 325.246us 50 50 100.00
lc_ctrl_sec_cm 9.110s 244.912us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 15.910s 325.246us 50 50 100.00
lc_ctrl_sec_cm 9.110s 244.912us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 11.110s 1780.628us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 8.910s 115.929us 50 50 100.00
lc_ctrl_jtag_state_post_trans 33.600s 2831.103us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 13.240s 1275.794us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 13.240s 1275.794us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 18.090s 3755.338us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 11.510s 1657.172us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 11.510s 1657.172us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 21 50 42.00
lc_ctrl_stress_all_with_rand_reset 127.530s 25018.927us 21 50 42.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 94086586060060013653481088567483459210205369207031099067156846099887824252013 205
UVM_ERROR @ 424354918 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 424354918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92129471064050876730111764101144733931083163067023427862616202051430880384812 4564
UVM_ERROR @ 1764737908 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1764737908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 40476808764976412073499195634201245483042406848217230854630703431835195056269 12584
UVM_ERROR @ 7198595469 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7198595469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108922752301853690037383257772283720040738362137316224847849425109743073419725 259
UVM_ERROR @ 127354193 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 127354193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 99023924144655857856812550920210729573964002092620227993725877391469972540696 27502
UVM_ERROR @ 10098228998 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10098228998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 61323126028556098913110477629257922271549530322746611726256035250135105195312 6579
UVM_ERROR @ 2209396303 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2209396303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 41472043234236014994445410830195887587729581673524625774876034814399134241151 4516
UVM_ERROR @ 1722377694 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1722377694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 57911910838414996045506415849855084322267553752487844561223897554532098670421 4997
UVM_ERROR @ 895669945 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 895669945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 104618303682495925424159796570266497275482511545874773544977885467247360841513 167
UVM_ERROR @ 1707464701 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1707464701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96240726601895945952311962387035111662071193025125031643142525400358483639525 244
UVM_ERROR @ 119648773 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 119648773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 99362431443742305264800915681258531194498787194312380755717473019588128861007 155
UVM_ERROR @ 3972193351 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3972193351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 53371885323114559904264994640440412319116186451104192281634479433480601225271 3167
UVM_ERROR @ 5280044206 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5280044206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 77779309237760155163388472633600351398503648435576983502634034371394538001948 3924
UVM_ERROR @ 5323924974 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5323924974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101648005122544386014788438740245949001576458676198196508971448523757370365321 150
UVM_ERROR @ 192291526 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 192291526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 31377382677282096011167153692914623329830075676361833759546347857378927011217 199
UVM_ERROR @ 113080275 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 113080275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47561824622207522992216166366672649535676437836488817658077730744964823969229 2871
UVM_ERROR @ 2131836943 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2131836943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 15612102110873941233219734777210735390552608152062583766353666462280522015505 2085
UVM_ERROR @ 10214057029 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10214057029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 106524738498150664814182162590006219705122081074467615229744060840902452769125 8135
UVM_ERROR @ 4320932082 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4320932082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 23835634020118383233883475928295521605911509045223516894766376818058233807902 8042
UVM_ERROR @ 9863531536 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9863531536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101649441753891774058265815729375790844772579589259877128378713373900749641452 3066
UVM_ERROR @ 9066616825 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9066616825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 112086385910237075074336024769917456527303937777260375554642716019110342359468 158
UVM_ERROR @ 1112048248 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1112048248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29796035201843769010807342841582677064977362866431275281336786296197478390927 162
UVM_ERROR @ 1910787243 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1910787243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93891483072752500941174793614927129056596565671225340445251086221302216507466 202
UVM_ERROR @ 528395098 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 528395098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 72863575963505679655633000641114882263212923326114930359362105309429592856180 747
UVM_ERROR @ 6721560818 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6721560818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 41986394675544203713419615737476444525305875870540571804226342485892014252954 2071
UVM_ERROR @ 28445613348 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 28445613348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 82415163475352667914879717553855162730539396991081735415460248977886328421533 7719
UVM_ERROR @ 5794433446 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5794433446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 15472070817344191529595459088098137445435123492183156227968498919435798421175 5142
UVM_ERROR @ 5325269728 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 5325269728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 58300158759637255264467499325250808976619562779726269187759520572384947034678 13361
UVM_ERROR @ 13660557857 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 13660557857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked*
lc_ctrl_stress_all_with_rand_reset 34370381704895253487190487497130987942869447549393435352527370098211395733369 4908
UVM_ERROR @ 10224939304 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 105, LC_St DecLcStTestUnlocked0
UVM_INFO @ 10224939304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---