Simulation Results: lc_ctrl/volatile_unlock_enabled

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.86 %
  • code
  • 89.36 %
  • assert
  • 95.99 %
  • func
  • 96.22 %
  • line
  • 97.87 %
  • branch
  • 97.06 %
  • cond
  • 82.35 %
  • toggle
  • 91.35 %
  • FSM
  • 78.18 %
Validation stages
V1
100.00%
V2
99.86%
V2S
100.00%
V3
46.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 7.490s 160.119us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.270s 52.903us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.330s 48.311us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.810s 67.236us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.260s 67.491us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.750s 41.692us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.330s 48.311us 20 20 100.00
lc_ctrl_csr_aliasing 1.260s 67.491us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 9.090s 85.085us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 16.680s 343.067us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.370s 15.936us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 5.070s 138.269us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 15.210s 352.751us 50 50 100.00
lc_errors 49 50 98.00
lc_ctrl_errors 13.490s 2201.524us 49 50 98.00
security_escalation 259 260 99.62
lc_ctrl_state_failure 15.210s 352.751us 50 50 100.00
lc_ctrl_prog_failure 5.070s 138.269us 50 50 100.00
lc_ctrl_errors 13.490s 2201.524us 49 50 98.00
lc_ctrl_security_escalation 11.130s 1326.545us 50 50 100.00
lc_ctrl_jtag_state_failure 59.250s 5700.806us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.580s 634.186us 20 20 100.00
lc_ctrl_jtag_errors 98.370s 5153.980us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_csr_hw_reset 3.400s 678.294us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.630s 220.099us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 26.240s 1659.799us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 18.370s 1100.716us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.780s 50.299us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.980s 248.106us 10 10 100.00
lc_ctrl_jtag_alert_test 3.060s 804.944us 10 10 100.00
lc_ctrl_jtag_smoke 14.080s 2694.138us 20 20 100.00
lc_ctrl_jtag_state_post_trans 24.780s 3562.591us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.580s 634.186us 20 20 100.00
lc_ctrl_jtag_errors 98.370s 5153.980us 20 20 100.00
lc_ctrl_jtag_access 21.350s 1800.381us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 25.400s 1213.981us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 22.020s 5590.447us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.590s 48.091us 50 50 100.00
stress_all 50 50 100.00
lc_ctrl_stress_all 686.700s 60555.213us 50 50 100.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.810s 172.780us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.760s 146.331us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.760s 146.331us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.270s 52.903us 5 5 100.00
lc_ctrl_csr_rw 1.330s 48.311us 20 20 100.00
lc_ctrl_csr_aliasing 1.260s 67.491us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.850s 42.313us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.270s 52.903us 5 5 100.00
lc_ctrl_csr_rw 1.330s 48.311us 20 20 100.00
lc_ctrl_csr_aliasing 1.260s 67.491us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.850s 42.313us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 3.700s 426.750us 20 20 100.00
lc_ctrl_sec_cm 9.790s 274.025us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.700s 426.750us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 16.680s 343.067us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 15.210s 352.751us 50 50 100.00
lc_ctrl_sec_cm 9.790s 274.025us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 15.210s 352.751us 50 50 100.00
lc_ctrl_sec_cm 9.790s 274.025us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 15.210s 352.751us 50 50 100.00
lc_ctrl_sec_cm 9.790s 274.025us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 15.210s 352.751us 50 50 100.00
lc_ctrl_sec_cm 9.790s 274.025us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 15.210s 352.751us 50 50 100.00
lc_ctrl_sec_cm 9.790s 274.025us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 15.210s 352.751us 50 50 100.00
lc_ctrl_sec_cm 9.790s 274.025us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 15.210s 352.751us 50 50 100.00
lc_ctrl_sec_cm 9.790s 274.025us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 15.210s 352.751us 50 50 100.00
lc_ctrl_sec_cm 9.790s 274.025us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 11.130s 1326.545us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 9.090s 85.085us 50 50 100.00
lc_ctrl_jtag_state_post_trans 24.780s 3562.591us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.490s 536.665us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.490s 536.665us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 21.520s 914.945us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 14.240s 509.240us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 14.240s 509.240us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 23 50 46.00
lc_ctrl_stress_all_with_rand_reset 127.130s 5772.886us 23 50 46.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 47625415498400258236178570615661700716174814343629558073942606024726582476321 694
UVM_ERROR @ 1173112597 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1173112597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 42907397757048371934380544581070747030296260663481528866443222498026878099350 1862
UVM_ERROR @ 3679717092 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3679717092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69350512442580629941234284005980560192140018581052047948005991130527726697957 1291
UVM_ERROR @ 786172800 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 786172800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 115614478656672289072914939890230428382594439314572236947897836863963049557494 8933
UVM_ERROR @ 2244642142 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2244642142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91247688909982453668522482796948374097099450970458625697386674099795029886159 194
UVM_ERROR @ 218630363 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 218630363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47604325894110878515257167029618012376772672989901234045554179495851122551446 11518
UVM_ERROR @ 30346471996 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 30346471996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 95079955850546597040019554538977548580100721241491466063223288621952690372522 1236
UVM_ERROR @ 3202487177 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3202487177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13320245041251958658803605973811681198660618397266622794041168018780015552109 3291
UVM_ERROR @ 2217519707 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2217519707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29490020344231323666047438892249714872651934341833703040914103744029411884325 219
UVM_ERROR @ 2359644085 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2359644085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 109428130595151899457537543070189436870026178697070963145343018499966822940614 1728
UVM_ERROR @ 1750916690 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1750916690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16667620653167544638658899164421212277030869944438158603353927429261330119800 6334
UVM_ERROR @ 5410476663 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5410476663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 103841272988495162478255026117432588922416811102256586134765597042588400347035 151
UVM_ERROR @ 114246126 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 114246126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 63517837329316056247602514785380500283806580106497086191760277708251065119240 3280
UVM_ERROR @ 2620344914 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2620344914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 94936374028466047055758019386942638369833252184975139873323751880030087951268 3394
UVM_ERROR @ 3471236402 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3471236402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105175479551000608490554962443246602074530956368082097703009533972279271158268 7678
UVM_ERROR @ 8559080334 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8559080334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60435981543971348876717279167559982363126084584793444312436821146532334179777 3510
UVM_ERROR @ 1551789574 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1551789574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37893170398530187155571035054758570845734236467752507460402281047392084683205 5642
UVM_ERROR @ 10153120668 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10153120668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 31951177663788270862785469107785678321382765401497941920228533214655593053856 3214
UVM_ERROR @ 1109647484 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1109647484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 90000812049033277249718865472710868171325131221330241379007565882181654897069 151
UVM_ERROR @ 110376021 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 110376021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101609903148952920451349286331073319185346613494794463694459083476769700276673 11980
UVM_ERROR @ 15846595241 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15846595241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 44759971085080935646566483078735480802412614730812635214563237929703659954237 5776
UVM_ERROR @ 1734052197 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1734052197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 28957703858719614262437681445468623309034116521329125385374651912697152381949 1271
UVM_ERROR @ 33115672675 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 33115672675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked*
lc_ctrl_stress_all_with_rand_reset 69907770871592125326911969682851407684906396799054000847667416013287878149627 6053
UVM_ERROR @ 6365666059 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 105, LC_St DecLcStTestUnlocked6
UVM_INFO @ 6365666059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 50255614920306313253268914533610745079030814770217498357768307167452326538647 1712
UVM_ERROR @ 1223366340 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 1223366340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 86231768475536221568970223371387102024188208581022269300782474765630305267833 11304
UVM_ERROR @ 3331717950 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 3331717950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 21711367485073334524857212563557667799196471383770820771727925687315771974795 4084
UVM_ERROR @ 3605320265 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 3605320265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92846180029331416004543170913935505783945382799289751503620588507197653156195 23324
UVM_ERROR @ 20053922558 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 20053922558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_errors 91712523778308500474452120669416658108542759828204896725164028544024090187906 469
UVM_ERROR @ 25829950 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25829950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---