Simulation Results: rom_ctrl/32kb

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.65%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.220s 436.834us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 6.780s 177.665us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 6.990s 660.803us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 5.860s 126.625us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 8.820s 2185.609us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.220s 185.959us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 6.990s 660.803us 20 20 100.00
rom_ctrl_csr_aliasing 8.820s 2185.609us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 4.250s 205.875us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 4.780s 582.370us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.440s 296.712us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 27.010s 2162.766us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 8.370s 1048.195us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 9.390s 533.399us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 10.270s 344.799us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 10.270s 344.799us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 6.780s 177.665us 5 5 100.00
rom_ctrl_csr_rw 6.990s 660.803us 20 20 100.00
rom_ctrl_csr_aliasing 8.820s 2185.609us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.520s 548.985us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 6.780s 177.665us 5 5 100.00
rom_ctrl_csr_rw 6.990s 660.803us 20 20 100.00
rom_ctrl_csr_aliasing 8.820s 2185.609us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.520s 548.985us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.930s 50887.338us 17 20 85.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 30.320s 6062.199us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 286.370s 2570.941us 5 5 100.00
rom_ctrl_tl_intg_err 68.420s 315.606us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 286.370s 2570.941us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 286.370s 2570.941us 5 5 100.00
sec_cm_checker_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.930s 50887.338us 17 20 85.00
sec_cm_checker_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.930s 50887.338us 17 20 85.00
sec_cm_checker_fsm_local_esc 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.930s 50887.338us 17 20 85.00
sec_cm_compare_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.930s 50887.338us 17 20 85.00
sec_cm_compare_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.930s 50887.338us 17 20 85.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 286.370s 2570.941us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 286.370s 2570.941us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.220s 436.834us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.220s 436.834us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.220s 436.834us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 68.420s 315.606us 20 20 100.00
sec_cm_bus_local_esc 19 22 86.36
rom_ctrl_corrupt_sig_fatal_chk 160.930s 50887.338us 17 20 85.00
rom_ctrl_kmac_err_chk 8.370s 1048.195us 2 2 100.00
sec_cm_mux_mubi 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.930s 50887.338us 17 20 85.00
sec_cm_mux_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.930s 50887.338us 17 20 85.00
sec_cm_ctrl_redun 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.930s 50887.338us 17 20 85.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 30.320s 6062.199us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 286.370s 2570.941us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 582.630s 28892.685us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 79924277328282760381503907772593462312269051050070197024906709707295195727661 90
UVM_ERROR @ 859747379 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 859747379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 42182335965376153716951337903755872303817807181670613622568648933636232914767 88
UVM_ERROR @ 7409648905 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 7409648905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 57581194467347087790740182955151932006043311044968061349771143576041531472501 80
UVM_ERROR @ 1077480320 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1077480320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---