Simulation Results: rom_ctrl/64kb

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.31%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 12.080s 1111.493us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 12.330s 308.095us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 14.580s 1066.824us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 10.650s 213.871us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 10.000s 300.342us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 12.410s 3995.892us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 14.580s 1066.824us 20 20 100.00
rom_ctrl_csr_aliasing 10.000s 300.342us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 9.680s 294.400us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 12.310s 7607.798us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 8.430s 219.131us 2 2 100.00
stress_all 19 20 95.00
rom_ctrl_stress_all 57.910s 1132.220us 19 20 95.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 20.280s 2103.512us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 12.770s 286.562us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 16.650s 1114.635us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 16.650s 1114.635us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 12.330s 308.095us 5 5 100.00
rom_ctrl_csr_rw 14.580s 1066.824us 20 20 100.00
rom_ctrl_csr_aliasing 10.000s 300.342us 5 5 100.00
rom_ctrl_same_csr_outstanding 13.610s 555.157us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 12.330s 308.095us 5 5 100.00
rom_ctrl_csr_rw 14.580s 1066.824us 20 20 100.00
rom_ctrl_csr_aliasing 10.000s 300.342us 5 5 100.00
rom_ctrl_same_csr_outstanding 13.610s 555.157us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.380s 7017.126us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 83.370s 20513.683us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_tl_intg_err 150.330s 658.153us 20 20 100.00
rom_ctrl_sec_cm 660.400s 696.577us 5 5 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 660.400s 696.577us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 660.400s 696.577us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.380s 7017.126us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.380s 7017.126us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.380s 7017.126us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.380s 7017.126us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.380s 7017.126us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 660.400s 696.577us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 660.400s 696.577us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 12.080s 1111.493us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 12.080s 1111.493us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 12.080s 1111.493us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 150.330s 658.153us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.380s 7017.126us 20 20 100.00
rom_ctrl_kmac_err_chk 20.280s 2103.512us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.380s 7017.126us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.380s 7017.126us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.380s 7017.126us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 83.370s 20513.683us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 660.400s 696.577us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 348.610s 5451.121us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
rom_ctrl_stress_all 11902749625926954917968824219929542815126753088405487334825964665069693064358 78
UVM_ERROR @ 1028946873 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
UVM_INFO @ 1028946873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---