Simulation Results

Simulation Results: spi_host

19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.81 %

code
95.03 %

assert
95.64 %

func
90.76 %

block
96.96 %

line
98.76 %

branch
93.35 %

toggle
88.02 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.74%
V2S		100.00%
unmapped		100.00%

115/115 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_host_smoke	102.000s	11667.771us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_host_csr_hw_reset	1.000s	40.298us	5	5	100.00
csr_rw				20	20	100.00
	spi_host_csr_rw	2.000s	40.153us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_host_csr_bit_bash	3.000s	583.199us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_host_csr_aliasing	2.000s	84.974us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_host_csr_mem_rw_with_rand_reset	2.000s	108.715us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_host_csr_rw	2.000s	40.153us	20	20	100.00
	spi_host_csr_aliasing	2.000s	84.974us	5	5	100.00
mem_walk				5	5	100.00
	spi_host_mem_walk	1.000s	31.064us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_host_mem_partial_access	2.000s	39.521us	5	5	100.00

768/770 passed

99.74 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
performance				50	50	100.00
	spi_host_performance	2.000s	64.158us	50	50	100.00
error_event_intr				150	150	100.00
	spi_host_overflow_underflow	23.000s	859.378us	50	50	100.00
	spi_host_error_cmd	2.000s	54.161us	50	50	100.00
	spi_host_event	559.000s	75836.381us	50	50	100.00
clock_rate				50	50	100.00
	spi_host_speed	10.000s	1028.387us	50	50	100.00
speed				50	50	100.00
	spi_host_speed	10.000s	1028.387us	50	50	100.00
chip_select_timing				50	50	100.00
	spi_host_speed	10.000s	1028.387us	50	50	100.00
sw_reset				50	50	100.00
	spi_host_sw_reset	227.000s	9269.844us	50	50	100.00
passthrough_mode				50	50	100.00
	spi_host_passthrough_mode	2.000s	171.746us	50	50	100.00
cpol_cpha				50	50	100.00
	spi_host_speed	10.000s	1028.387us	50	50	100.00
full_cycle				50	50	100.00
	spi_host_speed	10.000s	1028.387us	50	50	100.00
duplex				50	50	100.00
	spi_host_smoke	102.000s	11667.771us	50	50	100.00
tx_rx_only				50	50	100.00
	spi_host_smoke	102.000s	11667.771us	50	50	100.00
stress_all				50	50	100.00
	spi_host_stress_all	73.000s	24588.822us	50	50	100.00
spien				49	50	98.00
	spi_host_spien	74.000s	6126.363us	49	50	98.00
stall				49	50	98.00
	spi_host_status_stall	708.000s	23186.286us	49	50	98.00
Idlecsbactive				50	50	100.00
	spi_host_idlecsbactive	34.000s	1803.257us	50	50	100.00
data_fifo_status				50	50	100.00
	spi_host_overflow_underflow	23.000s	859.378us	50	50	100.00
alert_test				50	50	100.00
	spi_host_alert_test	2.000s	25.177us	50	50	100.00
intr_test				50	50	100.00
	spi_host_intr_test	2.000s	36.035us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_host_tl_errors	3.000s	436.838us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_host_tl_errors	3.000s	436.838us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_host_csr_hw_reset	1.000s	40.298us	5	5	100.00
	spi_host_csr_rw	2.000s	40.153us	20	20	100.00
	spi_host_csr_aliasing	2.000s	84.974us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	24.632us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_host_csr_hw_reset	1.000s	40.298us	5	5	100.00
	spi_host_csr_rw	2.000s	40.153us	20	20	100.00
	spi_host_csr_aliasing	2.000s	84.974us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	24.632us	20	20	100.00

V2S

25/25 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_host_sec_cm	2.000s	158.386us	5	5	100.00
	spi_host_tl_intg_err	2.000s	53.594us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_host_tl_intg_err	2.000s	53.594us	20	20	100.00

unmapped

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				10	10	100.00
	spi_host_upper_range_clkdiv	454.000s	38514.286us	10	10	100.00

Error Messages

	Test	seed	line	log context
xmsim: E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed
	spi_host_status_stall	264614040645987699740118911126042602146022001605476450725400919012555360621	1898	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 1126682961 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed UVM_ERROR @ 1126682961 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=1126683000 ps UVM_INFO @ 1126682961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = ns spi_host_reg_block.status.rxqd (addr=, Comparison=CompareOpEq, exp_data=, call_count=
	spi_host_spien	112680885617846515036146580168667224079676892377825805421703331923084840523010	310	UVM_FATAL @ 10358575298 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xc1ef7e54, Comparison=CompareOpEq, exp_data=0x0, call_count=47 UVM_INFO @ 10358575298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---