Simulation Results: ac_range_check

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
96.84%
V2
97.51%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 20 20 100.00
ac_range_check_smoke 51.000s 6261.168us 20 20 100.00
ac_range_check_smoke_racl 17 20 85.00
ac_range_check_smoke_racl 81.000s 6955.296us 17 20 85.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 3.000s 67.522us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 3.000s 257.809us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 50.000s 14796.015us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 35.000s 1307.864us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 4.000s 46.573us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 3.000s 257.809us 20 20 100.00
ac_range_check_csr_aliasing 35.000s 1307.864us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 23.351us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 39.000s 497.536us 1 1 100.00
stress_all 44 50 88.00
ac_range_check_stress_all 349.000s 22577.081us 44 50 88.00
alert_test 50 50 100.00
ac_range_check_alert_test 2.000s 27.113us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 2.000s 12.030us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 6.000s 1214.979us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 6.000s 1214.979us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 67.522us 5 5 100.00
ac_range_check_csr_rw 3.000s 257.809us 20 20 100.00
ac_range_check_csr_aliasing 35.000s 1307.864us 5 5 100.00
ac_range_check_same_csr_outstanding 7.000s 788.915us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 67.522us 5 5 100.00
ac_range_check_csr_rw 3.000s 257.809us 20 20 100.00
ac_range_check_csr_aliasing 35.000s 1307.864us 5 5 100.00
ac_range_check_same_csr_outstanding 7.000s 788.915us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 28.000s 7277.546us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 28.000s 7277.546us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 28.000s 7277.546us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 28.000s 7277.546us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 122.000s 7902.629us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 2.000s 12.152us 5 5 100.00
ac_range_check_tl_intg_err 16.000s 3038.639us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 434.000s 10465.986us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 59.000s 3223.910us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_smoke_racl 4030839120614096058234838852138524831965141972416628483420832984195232344020 4408
UVM_ERROR @ 1699148169 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1699148169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 5061552163580584111678200994783082727876104679636800108505701740654035203070 4038
UVM_ERROR @ 2162984749 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2162984749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 69754765242281462216698540395095941146330610037844584218404224762972749302509 4440
UVM_ERROR @ 1841966306 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1841966306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 82333832027578779564812713995748668334244655343669188965414491437163595594484 4341
UVM_ERROR @ 2338832751 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2338832751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 29612419235671755129626041103151841614103876986768955327760341611336201108444 4261
UVM_ERROR @ 2792303730 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2792303730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 106912770007613323617065086613938042079446235747441414485207890824221932381078 8330
UVM_ERROR @ 25706486243 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 25706486243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 47386503278029285797343650106245801023593029721671573931100914265872923723053 4323
UVM_ERROR @ 1306954247 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1306954247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 19072842560060867268047078752041812929141610207367132560223002996344437193464 13585
UVM_ERROR @ 5919389224 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 5919389224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_scoreboard.sv:166) [scoreboard] Unable to get any item from tl_unfilt_d_chan_fifo.
ac_range_check_stress_all 75781957228789602178835256131007728279424904147222464072268216326631388347196 20786
UVM_ERROR @ 100353143050 ps: (ac_range_check_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Unable to get any item from tl_unfilt_d_chan_fifo.
UVM_INFO @ 100353143050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---