Simulation Results

Simulation Results: csrng

20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.19 %

code
96.23 %

assert
95.85 %

func
90.50 %

block
98.59 %

line
99.57 %

branch
96.46 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		97.14%
V2S		100.00%
V3		0.00%

105/105 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	csrng_smoke	6.000s	264.633us	50	50	100.00
csr_hw_reset				5	5	100.00
	csrng_csr_hw_reset	3.000s	31.412us	5	5	100.00
csr_rw				20	20	100.00
	csrng_csr_rw	3.000s	14.732us	20	20	100.00
csr_bit_bash				5	5	100.00
	csrng_csr_bit_bash	34.000s	3229.357us	5	5	100.00
csr_aliasing				5	5	100.00
	csrng_csr_aliasing	5.000s	83.118us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	csrng_csr_mem_rw_with_rand_reset	5.000s	230.030us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	csrng_csr_rw	3.000s	14.732us	20	20	100.00
	csrng_csr_aliasing	5.000s	83.118us	5	5	100.00

1428/1470 passed

97.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	47.000s	4046.100us	500	500	100.00
err				500	500	100.00
	csrng_err	4.000s	52.364us	500	500	100.00
cmds				8	50	16.00
	csrng_cmds	114.000s	8840.516us	8	50	16.00
life cycle				8	50	16.00
	csrng_cmds	114.000s	8840.516us	8	50	16.00
stress_all				50	50	100.00
	csrng_stress_all	842.000s	20107.277us	50	50	100.00
intr_test				50	50	100.00
	csrng_intr_test	4.000s	191.016us	50	50	100.00
alert_test				50	50	100.00
	csrng_alert_test	4.000s	124.253us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	csrng_tl_errors	16.000s	1384.180us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	csrng_tl_errors	16.000s	1384.180us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	csrng_csr_hw_reset	3.000s	31.412us	5	5	100.00
	csrng_csr_rw	3.000s	14.732us	20	20	100.00
	csrng_csr_aliasing	5.000s	83.118us	5	5	100.00
	csrng_same_csr_outstanding	5.000s	80.931us	20	20	100.00
tl_d_partial_access				50	50	100.00
	csrng_csr_hw_reset	3.000s	31.412us	5	5	100.00
	csrng_csr_rw	3.000s	14.732us	20	20	100.00
	csrng_csr_aliasing	5.000s	83.118us	5	5	100.00
	csrng_same_csr_outstanding	5.000s	80.931us	20	20	100.00

V2S

1345/1345 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	csrng_tl_intg_err	20.000s	530.411us	20	20	100.00
	csrng_sec_cm	14.000s	391.464us	5	5	100.00
sec_cm_config_regwen				70	70	100.00
	csrng_csr_rw	3.000s	14.732us	20	20	100.00
	csrng_regwen	3.000s	44.702us	50	50	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	47.000s	4046.100us	500	500	100.00
sec_cm_intersig_mubi				50	50	100.00
	csrng_stress_all	842.000s	20107.277us	50	50	100.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
	csrng_err	4.000s	52.364us	500	500	100.00
	csrng_sec_cm	14.000s	391.464us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
	csrng_err	4.000s	52.364us	500	500	100.00
	csrng_sec_cm	14.000s	391.464us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
	csrng_err	4.000s	52.364us	500	500	100.00
	csrng_sec_cm	14.000s	391.464us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
	csrng_err	4.000s	52.364us	500	500	100.00
	csrng_sec_cm	14.000s	391.464us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
	csrng_err	4.000s	52.364us	500	500	100.00
	csrng_sec_cm	14.000s	391.464us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	47.000s	4046.100us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
	csrng_err	4.000s	52.364us	500	500	100.00
sec_cm_constants_lc_gated				50	50	100.00
	csrng_stress_all	842.000s	20107.277us	50	50	100.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	47.000s	4046.100us	500	500	100.00
sec_cm_tile_link_bus_integrity				20	20	100.00
	csrng_tl_intg_err	20.000s	530.411us	20	20	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
	csrng_err	4.000s	52.364us	500	500	100.00
	csrng_sec_cm	14.000s	391.464us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
	csrng_err	4.000s	52.364us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
	csrng_err	4.000s	52.364us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
	csrng_err	4.000s	52.364us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
	csrng_err	4.000s	52.364us	500	500	100.00
	csrng_sec_cm	14.000s	391.464us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	17.000s	1211.224us	200	200	100.00
	csrng_err	4.000s	52.364us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	0.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])
	csrng_cmds	89099067727736421563640993745962871632448001114209479926832797740817207190211	130	UVM_FATAL @ 716722231 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 231847583322161455745118791155276785963 [0xae6c38673ec4a2d484a04f79c61f292b]) UVM_INFO @ 716722231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	79918435165639880687651986522726958535510254718457159996247827702267425354603	140	UVM_FATAL @ 116718067 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 132061933844905455898296986457842497692 [0x635a340ad99e4ff33e84e1b446f5b89c]) UVM_INFO @ 116718067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	4857553573109574975694749327559730952671768438216353367379193162018595487197	130	UVM_FATAL @ 104368729 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 226385402638828530796054987028540135988 [0xaa503e1a78c9fdee04ad8d0e0d939a34]) UVM_INFO @ 104368729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	66420291681541204052688683011640683888042149609526514029087287453262272404902	130	UVM_FATAL @ 23768792 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 71347069954715867036850884674341239822 [0x35acf223078d965f08980c4963defc0e]) UVM_INFO @ 23768792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	47021851417293277069605218462199826413636339496246256137772641778596667086978	130	UVM_FATAL @ 42919675 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 254139447084607304581746551881869557684 [0xbf317a2478f53bc684caf16f102fffb4]) UVM_INFO @ 42919675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	61830610628439487912452123715082575070520045082632400860344730892490423225487	130	UVM_FATAL @ 138260288 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 336101046620313315659319728365518335816 [0xfcdab4fe1f407afc5a6a9c4731a22f48]) UVM_INFO @ 138260288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	11254890138957805333144582329661944473757266380385681324718102284809646186033	130	UVM_FATAL @ 482536389 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 201992006599479302150227025626998017931 [0x97f63ed2c68c7f6eebe8583c28788f8b]) UVM_INFO @ 482536389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	93839226417288552905132145127539199842189015778067269950267636953296622303013	130	UVM_FATAL @ 376513619 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 162486934918858993993676953949851671068 [0x7a3dd869111db98d0da4f1ffbdb8da1c]) UVM_INFO @ 376513619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	8953191080090718105070853234870294701294489427132696162888753182378084698972	130	UVM_FATAL @ 111765408 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 274199787817261956400114235418420056191 [0xce48f54d4350f5da8ecddbd13672107f]) UVM_INFO @ 111765408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	20003075790759337038945488762804412402462453929718993891442493931441477853643	130	UVM_FATAL @ 149997394 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 257174485648297552217806663987140919482 [0xc17a0118c5b09805a21910128c6680ba]) UVM_INFO @ 149997394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	18134166121730522971138881606599999228225063247616209208046783791484845867767	130	UVM_FATAL @ 279851628 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 316315190309285481865795325056727616965 [0xedf816f5ccf649d44d3344b687bb8dc5]) UVM_INFO @ 279851628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	114142275714613511017238634376030267121885867401737214873409824961724147591214	139	UVM_FATAL @ 42627793 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (97922883241133045816388558486296330588 [0x49ab42e50c170a74f9314f29f408015c] vs 142553817258719536456411016320904110661 [0x6b3eddd534effe9e6efb78501480a245]) UVM_INFO @ 42627793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	69035693395210387477518502309525744809834585859762996451725248021020602231287	130	UVM_FATAL @ 69188562 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 106747308676442970167207974542752375962 [0x504ec8a8d6a738d28279b26dfd90649a]) UVM_INFO @ 69188562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	100254284741310320922271315302743927717632462621919547851185104287321381397597	130	UVM_FATAL @ 160744265 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 146977334652860788586634194831474343208 [0x6e92ce142dfcba719754d2767bd2bd28]) UVM_INFO @ 160744265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	48829029123828800193987940889834594705984064725337784178804266047274765016201	130	UVM_FATAL @ 77124256 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 107293912834716015948398671656622567457 [0x50b80e5341878d53e29d4d5270b13021]) UVM_INFO @ 77124256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	103545707333065815119985215544309064343585814811997636451040334491500654086325	130	UVM_FATAL @ 103285885 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 276830433118175733591224836580618259860 [0xd0439a20ff4c8ff938076361e73fcd94]) UVM_INFO @ 103285885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	79164231375805712647331155039449612414554103191332386997881149271881865967257	130	UVM_FATAL @ 401313097 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 3832279902831529565432655216283179513 [0x2e211fcb0fad78d815d7ff4c41b59f9]) UVM_INFO @ 401313097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	61667825039747110114119733682855621294285759756102507911607246070367296672211	130	UVM_FATAL @ 58476674 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 230820993181425376406947185723249001594 [0xada6819a0075aac465524f8a9f2c047a]) UVM_INFO @ 58476674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	103980492981929190163193471743272176581368492347482710004033545325562192765014	130	UVM_FATAL @ 167181592 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 282840042617896273842302780215895468041 [0xd4c902c0d63be4a0d1a03744acff2809]) UVM_INFO @ 167181592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	56182142654808940501772582558128832625423665299653985589232680355206213938243	139	UVM_FATAL @ 48639446 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 251310711873855204236465351678191116571 [0xbd10aeba9198fe48c011dfea18e6a11b]) UVM_INFO @ 48639446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	55082944715982395619981152171312043031295805588737451339864694055967770447187	130	UVM_FATAL @ 208729443 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 160765189359525381380824345855871284050 [0x78f23fcce61fb11e8409b1e8c8d5f352]) UVM_INFO @ 208729443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	60633983323162132323622318418039595837741212720589408733510442228917881460476	130	UVM_FATAL @ 144920716 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 73819136531637059869313389707084092812 [0x37890c6ddf27204055f389579156d58c]) UVM_INFO @ 144920716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	40976493953721798393301243794763398223511996112044281002987512131645541798377	130	UVM_FATAL @ 236732831 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 178471486329918874828378388578170161949 [0x86445ba4329f99937d70eea4a895cb1d]) UVM_INFO @ 236732831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	24125777600581742413355370206127416421463780808829012809074165845815354244091	130	UVM_FATAL @ 393067781 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 67014569046888824686185007248821145080 [0x326a89599f06aa7f21f27e085bd34df8]) UVM_INFO @ 393067781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	40991175159780326161638715634968762770151426295479690141527515528743534355447	130	UVM_FATAL @ 189522345 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 123030247954725892443229234026165440896 [0x5c8ec38c568d0b41883bf24980921180]) UVM_INFO @ 189522345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	54022857366692537889801442151939598512367279982811214500759557679677070918206	130	UVM_FATAL @ 197107637 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 313861850944460498123102567623293202046 [0xec1f97fd9b31e70aa12bf2818c24ee7e]) UVM_INFO @ 197107637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	42913262617862682415020294333551442559147042704134181057277576292072700223740	130	UVM_FATAL @ 467160530 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 330240313222859430257538873854989598005 [0xf871f886df0c96a6ae43e136288a7d35]) UVM_INFO @ 467160530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	35585234113012683840220084387088643406547921992372473567526394015711334737415	130	UVM_FATAL @ 171485797 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 177693119023386303322686213964469535853 [0x85ae732b96debcb5cc7beeed6d46846d]) UVM_INFO @ 171485797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	29247264719921195788066446462461201412220393068575238811713429687707860482310	150	UVM_FATAL @ 291991504 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 218568967551078670051401228096594947794 [0xa46eda198770155ec10739a1211eaed2]) UVM_INFO @ 291991504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	94746719697463788076550646239085313594733975882297966596310878555642742556272	130	UVM_FATAL @ 101820457 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 179502993620713155450945840932807326445 [0x870b04e099abba1c77c498b0bfa93aed]) UVM_INFO @ 101820457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	8049364064293405400523875551893835147358821935529049737328363367411323353451	130	UVM_FATAL @ 84811289 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 235515539373954750358028442004668374240 [0xb12ea49958b0993094884013518d5ce0]) UVM_INFO @ 84811289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	27400636806392634915502172718978539429132544206163222193410816587606460906901	130	UVM_FATAL @ 449593835 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 180759189839374880563615801608482585989 [0x87fcf421fab3213f323afc3012a3fd85]) UVM_INFO @ 449593835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	27901760890344632157371115126707713418428727309718401446162655450056503588075	130	UVM_FATAL @ 428079590 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 159299958834700353347977131589805585898 [0x77d80e5ba5ef87ed06594dc66858b5ea]) UVM_INFO @ 428079590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	58394931251750742662899566660352787423608297861466862409439482430669874255432	130	UVM_FATAL @ 40052882 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 164729978413993466049603195817781547281 [0x7bedd6fe381e243cefcb1c9b1342d111]) UVM_INFO @ 40052882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	79780882360092257278861996930509396577745694571625368121477990556450455996870	130	UVM_FATAL @ 56427106 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 21707032378207190020443489199783980206 [0x10549f536271d41bbf4a1a41e468acae]) UVM_INFO @ 56427106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	73459143164656523649409034461891504602850288249915990968148035089886950730202	130	UVM_FATAL @ 128546503 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 159505629301766263147529433991877538786 [0x77ffaab1e6c32d72cd3445b7b4acb3e2]) UVM_INFO @ 128546503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	65330292035742411463264272391765528401131793131179978836313806692818209399040	130	UVM_FATAL @ 14162664 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 102792483453239418070422328103498096695 [0x4d551cb8bfd98b185b90414809432037]) UVM_INFO @ 14162664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	95567296962530694144882268092743217388782416764288628462621640974392999236059	130	UVM_FATAL @ 54277859 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 304691765727895517988452891577358536589 [0xe5397fe202083802ee11402e0c48cf8d]) UVM_INFO @ 54277859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	73918868007133172979711879309670883862232074903665825850524116144050829632564	130	UVM_FATAL @ 73064750 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 75992203352450629286223528553348169066 [0x392b90e538be5ad1a003cc8eb6517d6a]) UVM_INFO @ 73064750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	87235344570256933979409355648558791175584234023603842014578161302760566093175	130	UVM_FATAL @ 33374728 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 261389862429474487927025063002086509908 [0xc4a5db37de0c577428a824f2efdb0d54]) UVM_INFO @ 33374728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	csrng_stress_all_with_rand_reset	101604281183844011637337856050693996773973353607172980019421798870400382199477	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	85708931009918416191477142679570834895123341083688834015331064151309328158345	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	91572031806654471749472960401278253325068276758934930471910924445140244280616	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	112808469821279468974213100143704530378364985723212407078579069833282133231317	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	94357793499509377448458522011729920049086305416789456103102961743105941769128	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	10279411737308554907579407300899958874440205226452646336857404038142241923138	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	46284606043126644095329896764918343227702651502265445820169740786546572188118	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	43022971474626296227234854277609109599607610808788134483843070889975489321691	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	111838331391013749328808911986263047508116865521572819885821948214145133215630	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	9963599599341582306766151531686088840866916845199421980225000284328543231113	None	Job timed out after 180 minutes
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits
	csrng_cmds	44171999018396045174562276845554129909233276900774280531646601727450687164181	133	UVM_ERROR @ 383858293 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1523143317 [0x5ac95295] vs 3613619883 [0xd76376ab]) reg name: csrng_reg_block.genbits UVM_INFO @ 383858293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	58559392195184685970679923683974106957017444497872337981225296672227064248323	133	UVM_ERROR @ 193389377 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1176661796 [0x46226f24] vs 565440655 [0x21b3f08f]) reg name: csrng_reg_block.genbits UVM_INFO @ 193389377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---