Simulation Results: hmac

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.04 %
  • code
  • 99.32 %
  • assert
  • 97.80 %
  • func
  • 100.00 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.85 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 16.580s 5344.190us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.380s 114.873us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.280s 120.892us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 15.100s 1623.501us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 6.880s 2223.211us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 886.990s 104316.032us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.280s 120.892us 20 20 100.00
hmac_csr_aliasing 6.880s 2223.211us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 75.090s 26715.643us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 110.100s 17285.501us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 271.750s 30865.911us 30 30 100.00
hmac_test_sha384_vectors 557.350s 14048.884us 75 75 100.00
hmac_test_sha512_vectors 562.080s 63749.311us 75 75 100.00
hmac_test_hmac256_vectors 16.590s 386.184us 50 50 100.00
hmac_test_hmac384_vectors 17.980s 2202.451us 60 60 100.00
hmac_test_hmac512_vectors 18.780s 2234.262us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 44.730s 3036.750us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1054.730s 5612.578us 10 10 100.00
error 10 10 100.00
hmac_error 99.040s 7031.279us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 112.660s 139257.247us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 16.580s 5344.190us 10 10 100.00
hmac_long_msg 75.090s 26715.643us 10 10 100.00
hmac_back_pressure 110.100s 17285.501us 25 25 100.00
hmac_datapath_stress 1054.730s 5612.578us 10 10 100.00
hmac_burst_wr 44.730s 3036.750us 50 50 100.00
hmac_stress_all 2315.300s 230189.828us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 16.580s 5344.190us 10 10 100.00
hmac_long_msg 75.090s 26715.643us 10 10 100.00
hmac_back_pressure 110.100s 17285.501us 25 25 100.00
hmac_datapath_stress 1054.730s 5612.578us 10 10 100.00
hmac_wipe_secret 112.660s 139257.247us 10 10 100.00
hmac_test_sha256_vectors 271.750s 30865.911us 30 30 100.00
hmac_test_sha384_vectors 557.350s 14048.884us 75 75 100.00
hmac_test_sha512_vectors 562.080s 63749.311us 75 75 100.00
hmac_test_hmac256_vectors 16.590s 386.184us 50 50 100.00
hmac_test_hmac384_vectors 17.980s 2202.451us 60 60 100.00
hmac_test_hmac512_vectors 18.780s 2234.262us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 16.580s 5344.190us 10 10 100.00
hmac_long_msg 75.090s 26715.643us 10 10 100.00
hmac_back_pressure 110.100s 17285.501us 25 25 100.00
hmac_datapath_stress 1054.730s 5612.578us 10 10 100.00
hmac_burst_wr 44.730s 3036.750us 50 50 100.00
hmac_error 99.040s 7031.279us 10 10 100.00
hmac_wipe_secret 112.660s 139257.247us 10 10 100.00
hmac_test_sha256_vectors 271.750s 30865.911us 30 30 100.00
hmac_test_sha384_vectors 557.350s 14048.884us 75 75 100.00
hmac_test_sha512_vectors 562.080s 63749.311us 75 75 100.00
hmac_test_hmac256_vectors 16.590s 386.184us 50 50 100.00
hmac_test_hmac384_vectors 17.980s 2202.451us 60 60 100.00
hmac_test_hmac512_vectors 18.780s 2234.262us 75 75 100.00
hmac_stress_all 2315.300s 230189.828us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2315.300s 230189.828us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.940s 15.147us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.980s 43.131us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.740s 962.878us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.740s 962.878us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.380s 114.873us 5 5 100.00
hmac_csr_rw 1.280s 120.892us 20 20 100.00
hmac_csr_aliasing 6.880s 2223.211us 5 5 100.00
hmac_same_csr_outstanding 2.730s 990.464us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.380s 114.873us 5 5 100.00
hmac_csr_rw 1.280s 120.892us 20 20 100.00
hmac_csr_aliasing 6.880s 2223.211us 5 5 100.00
hmac_same_csr_outstanding 2.730s 990.464us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.540s 101.481us 5 5 100.00
hmac_tl_intg_err 4.870s 226.581us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.870s 226.581us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 16.580s 5344.190us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 9.150s 167.023us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 376.830s 19206.366us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.380s 165.074us 1 1 100.00