Simulation Results: keymgr_dpe

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.39 %
  • code
  • 84.21 %
  • assert
  • 97.64 %
  • func
  • 17.32 %
  • line
  • 97.67 %
  • branch
  • 94.50 %
  • cond
  • 90.03 %
  • toggle
  • 63.15 %
  • FSM
  • 75.68 %
Validation stages
V1
99.05%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_dpe_smoke 278.030s 15989.444us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_dpe_csr_hw_reset 1.450s 22.320us 5 5 100.00
csr_rw 20 20 100.00
keymgr_dpe_csr_rw 1.690s 43.591us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_dpe_csr_bit_bash 13.290s 2482.805us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_dpe_csr_aliasing 5.760s 320.406us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.220s 416.357us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_dpe_csr_rw 1.690s 43.591us 20 20 100.00
keymgr_dpe_csr_aliasing 5.760s 320.406us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 50 50 100.00
keymgr_dpe_intr_test 1.280s 30.136us 50 50 100.00
alert_test 50 50 100.00
keymgr_dpe_alert_test 1.340s 32.627us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_dpe_tl_errors 4.630s 680.358us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_dpe_tl_errors 4.630s 680.358us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_dpe_csr_hw_reset 1.450s 22.320us 5 5 100.00
keymgr_dpe_csr_rw 1.690s 43.591us 20 20 100.00
keymgr_dpe_csr_aliasing 5.760s 320.406us 5 5 100.00
keymgr_dpe_same_csr_outstanding 2.880s 134.659us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_dpe_csr_hw_reset 1.450s 22.320us 5 5 100.00
keymgr_dpe_csr_rw 1.690s 43.591us 20 20 100.00
keymgr_dpe_csr_aliasing 5.760s 320.406us 5 5 100.00
keymgr_dpe_same_csr_outstanding 2.880s 134.659us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
keymgr_dpe_tl_intg_err 9.330s 459.429us 20 20 100.00
keymgr_dpe_sec_cm 13.200s 4370.879us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.520s 238.553us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.520s 238.553us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.520s 238.553us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.520s 238.553us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 8.880s 628.935us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 13.200s 4370.879us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 13.200s 4370.879us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.debug reset value: *
keymgr_dpe_csr_mem_rw_with_rand_reset 23753243856410167952098104630322234453089574415133194439744259492268935292884 88
UVM_ERROR @ 13513301 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (256 [0x100] vs 0 [0x0]) Regname: keymgr_dpe_reg_block.debug reset value: 0x0
UVM_INFO @ 13513301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---