| V1 |
|
100.00% |
| V2 |
|
97.92% |
| V2S |
|
100.00% |
| V3 |
|
90.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| kmac_smoke | 69.350s | 49050.011us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| kmac_csr_hw_reset | 1.510s | 36.609us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| kmac_csr_rw | 1.530s | 245.567us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| kmac_csr_bit_bash | 14.780s | 298.752us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| kmac_csr_aliasing | 10.010s | 1920.864us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| kmac_csr_mem_rw_with_rand_reset | 2.810s | 719.495us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| kmac_csr_rw | 1.530s | 245.567us | 20 | 20 | 100.00 | |
| kmac_csr_aliasing | 10.010s | 1920.864us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| kmac_mem_walk | 1.080s | 22.894us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| kmac_mem_partial_access | 1.640s | 105.969us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| long_msg_and_output | 50 | 50 | 100.00 | |||
| kmac_long_msg_and_output | 3378.870s | 486763.195us | 50 | 50 | 100.00 | |
| burst_write | 50 | 50 | 100.00 | |||
| kmac_burst_write | 867.830s | 150133.599us | 50 | 50 | 100.00 | |
| test_vectors | 40 | 40 | 100.00 | |||
| kmac_test_vectors_sha3_224 | 1897.730s | 153180.787us | 5 | 5 | 100.00 | |
| kmac_test_vectors_sha3_256 | 1579.030s | 57789.957us | 5 | 5 | 100.00 | |
| kmac_test_vectors_sha3_384 | 1458.150s | 68441.146us | 5 | 5 | 100.00 | |
| kmac_test_vectors_sha3_512 | 798.060s | 31416.198us | 5 | 5 | 100.00 | |
| kmac_test_vectors_shake_128 | 2231.250s | 212061.556us | 5 | 5 | 100.00 | |
| kmac_test_vectors_shake_256 | 1756.240s | 118269.817us | 5 | 5 | 100.00 | |
| kmac_test_vectors_kmac | 2.470s | 127.761us | 5 | 5 | 100.00 | |
| kmac_test_vectors_kmac_xof | 3.860s | 1692.582us | 5 | 5 | 100.00 | |
| sideload | 50 | 50 | 100.00 | |||
| kmac_sideload | 435.130s | 88569.783us | 50 | 50 | 100.00 | |
| app | 50 | 50 | 100.00 | |||
| kmac_app | 320.640s | 75589.686us | 50 | 50 | 100.00 | |
| app_with_partial_data | 10 | 10 | 100.00 | |||
| kmac_app_with_partial_data | 246.160s | 47887.669us | 10 | 10 | 100.00 | |
| entropy_refresh | 50 | 50 | 100.00 | |||
| kmac_entropy_refresh | 359.950s | 72935.923us | 50 | 50 | 100.00 | |
| error | 50 | 50 | 100.00 | |||
| kmac_error | 388.820s | 22014.871us | 50 | 50 | 100.00 | |
| key_error | 50 | 50 | 100.00 | |||
| kmac_key_error | 14.210s | 8125.186us | 50 | 50 | 100.00 | |
| sideload_invalid | 34 | 50 | 68.00 | |||
| kmac_sideload_invalid | 128.590s | 10150.862us | 34 | 50 | 68.00 | |
| edn_timeout_error | 20 | 20 | 100.00 | |||
| kmac_edn_timeout_error | 40.670s | 6225.205us | 20 | 20 | 100.00 | |
| entropy_mode_error | 20 | 20 | 100.00 | |||
| kmac_entropy_mode_error | 29.680s | 7265.663us | 20 | 20 | 100.00 | |
| entropy_ready_error | 10 | 10 | 100.00 | |||
| kmac_entropy_ready_error | 78.230s | 34017.053us | 10 | 10 | 100.00 | |
| lc_escalation | 50 | 50 | 100.00 | |||
| kmac_lc_escalation | 46.570s | 2956.341us | 50 | 50 | 100.00 | |
| stress_all | 50 | 50 | 100.00 | |||
| kmac_stress_all | 1759.380s | 70443.243us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| kmac_intr_test | 1.140s | 56.736us | 50 | 50 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| kmac_alert_test | 1.290s | 223.895us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| kmac_tl_errors | 4.380s | 183.506us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| kmac_tl_errors | 4.380s | 183.506us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| kmac_csr_hw_reset | 1.510s | 36.609us | 5 | 5 | 100.00 | |
| kmac_csr_rw | 1.530s | 245.567us | 20 | 20 | 100.00 | |
| kmac_csr_aliasing | 10.010s | 1920.864us | 5 | 5 | 100.00 | |
| kmac_same_csr_outstanding | 3.070s | 102.561us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| kmac_csr_hw_reset | 1.510s | 36.609us | 5 | 5 | 100.00 | |
| kmac_csr_rw | 1.530s | 245.567us | 20 | 20 | 100.00 | |
| kmac_csr_aliasing | 10.010s | 1920.864us | 5 | 5 | 100.00 | |
| kmac_same_csr_outstanding | 3.070s | 102.561us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| kmac_shadow_reg_errors | 2.960s | 223.969us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| kmac_shadow_reg_errors | 2.960s | 223.969us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| kmac_shadow_reg_errors | 2.960s | 223.969us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| kmac_shadow_reg_errors | 2.960s | 223.969us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| kmac_shadow_reg_errors_with_csr_rw | 4.990s | 88.150us | 20 | 20 | 100.00 | |
| tl_intg_err | 25 | 25 | 100.00 | |||
| kmac_sec_cm | 55.560s | 3193.325us | 5 | 5 | 100.00 | |
| kmac_tl_intg_err | 5.980s | 504.475us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| kmac_tl_intg_err | 5.980s | 504.475us | 20 | 20 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 50 | 50 | 100.00 | |||
| kmac_lc_escalation | 46.570s | 2956.341us | 50 | 50 | 100.00 | |
| sec_cm_sw_key_key_masking | 50 | 50 | 100.00 | |||
| kmac_smoke | 69.350s | 49050.011us | 50 | 50 | 100.00 | |
| sec_cm_key_sideload | 50 | 50 | 100.00 | |||
| kmac_sideload | 435.130s | 88569.783us | 50 | 50 | 100.00 | |
| sec_cm_cfg_shadowed_config_shadow | 20 | 20 | 100.00 | |||
| kmac_shadow_reg_errors | 2.960s | 223.969us | 20 | 20 | 100.00 | |
| sec_cm_fsm_sparse | 5 | 5 | 100.00 | |||
| kmac_sec_cm | 55.560s | 3193.325us | 5 | 5 | 100.00 | |
| sec_cm_ctr_redun | 5 | 5 | 100.00 | |||
| kmac_sec_cm | 55.560s | 3193.325us | 5 | 5 | 100.00 | |
| sec_cm_packer_ctr_redun | 5 | 5 | 100.00 | |||
| kmac_sec_cm | 55.560s | 3193.325us | 5 | 5 | 100.00 | |
| sec_cm_cfg_shadowed_config_regwen | 50 | 50 | 100.00 | |||
| kmac_smoke | 69.350s | 49050.011us | 50 | 50 | 100.00 | |
| sec_cm_fsm_global_esc | 50 | 50 | 100.00 | |||
| kmac_lc_escalation | 46.570s | 2956.341us | 50 | 50 | 100.00 | |
| sec_cm_fsm_local_esc | 5 | 5 | 100.00 | |||
| kmac_sec_cm | 55.560s | 3193.325us | 5 | 5 | 100.00 | |
| sec_cm_absorbed_ctrl_mubi | 10 | 10 | 100.00 | |||
| kmac_mubi | 342.110s | 17725.614us | 10 | 10 | 100.00 | |
| sec_cm_sw_cmd_ctrl_sparse | 50 | 50 | 100.00 | |||
| kmac_smoke | 69.350s | 49050.011us | 50 | 50 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 9 | 10 | 90.00 | |||
| kmac_stress_all_with_rand_reset | 246.750s | 8324.867us | 9 | 10 | 90.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) | ||||
| kmac_stress_all_with_rand_reset | 83662783577464227814224810217569635677655968312687516107216885110594078366203 | 357 |
UVM_ERROR @ 9554044090 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 9554044090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) | ||||
| kmac_sideload_invalid | 85407684375482734325488233619218114396590537012290977583318833163543430125804 | 78 |
UVM_FATAL @ 10008514962 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaae7000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10008514962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_sideload_invalid | 39172017591315529001098547513636339950335706757100912242566433530889150246216 | 78 |
UVM_FATAL @ 10017087150 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa7eb4000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10017087150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_sideload_invalid | 100023049699148966058462279093664741483606162683107268401242332203094258145519 | 78 |
UVM_FATAL @ 10009058950 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9d805000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10009058950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) | ||||
| kmac_sideload_invalid | 33422084174877582445346933150711961027373856196077583059419118889378141808409 | 97 |
UVM_FATAL @ 10492293252 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe300d000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 10492293252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) | ||||
| kmac_sideload_invalid | 92841763089857094341622741430250417693108246511569012545683546790257402559079 | 98 |
UVM_FATAL @ 10103736465 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x90409000, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10103736465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) | ||||
| kmac_sideload_invalid | 16468900188004144681275178152051826244907901330903238828119548199450019259202 | 90 |
UVM_FATAL @ 10109257824 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc0d46000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10109257824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_sideload_invalid | 70183184741903372287900885333168943131558475020051416433948910647674211608885 | 90 |
UVM_FATAL @ 10242356388 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfe1ab000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10242356388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) | ||||
| kmac_sideload_invalid | 79117534051906009243982488220236885462440886722057180476409028708368304180597 | 88 |
UVM_FATAL @ 10598063779 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb16dd000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10598063779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) | ||||
| kmac_sideload_invalid | 9857979972102979070447280144627024976975711229281790767647153333773945614846 | 82 |
UVM_FATAL @ 10177694176 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5fef5000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10177694176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) | ||||
| kmac_sideload_invalid | 3516316239762421079681386998879479342381947931821890256937692943798765843202 | 80 |
UVM_FATAL @ 10032940995 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc024a000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10032940995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_sideload_invalid | 1558357898618619455166755021419111520701445759510224133291991548615329536520 | 80 |
UVM_FATAL @ 10058592542 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x45f72000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10058592542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) | ||||
| kmac_sideload_invalid | 36777199703092152709319570511603916577004801638240366230642146621428715439542 | 86 |
UVM_FATAL @ 10206325428 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8e139000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10206325428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) | ||||
| kmac_sideload_invalid | 71326994737765692517454579164078003793666673261223066963376867834743408307846 | 90 |
UVM_FATAL @ 10292241375 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x398d0000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10292241375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) | ||||
| kmac_sideload_invalid | 7491780448401227524253516521518024247046094221877546104012201233493364789013 | 81 |
UVM_FATAL @ 10104582207 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x49ee2000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10104582207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) | ||||
| kmac_sideload_invalid | 58353940926957071803928683751942542996174048000508078985915915703054207715920 | 110 |
UVM_FATAL @ 10363390060 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3049c000, Comparison=CompareOpEq, exp_data=0x1, call_count=30)
UVM_INFO @ 10363390060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) | ||||
| kmac_sideload_invalid | 86623826145785277862870364630281117750382421264407512061178969102035888308727 | 108 |
UVM_FATAL @ 10150862465 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3a2c8000, Comparison=CompareOpEq, exp_data=0x1, call_count=27)
UVM_INFO @ 10150862465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|