Simulation Results: lc_ctrl/volatile_unlock_disabled

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.64 %
  • code
  • 88.70 %
  • assert
  • 95.99 %
  • func
  • 96.22 %
  • line
  • 97.90 %
  • branch
  • 96.99 %
  • cond
  • 82.70 %
  • toggle
  • 91.35 %
  • FSM
  • 74.55 %
Validation stages
V1
100.00%
V2
99.86%
V2S
100.00%
V3
46.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 5.840s 566.007us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.310s 69.705us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.360s 14.811us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.180s 201.744us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.570s 37.281us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.920s 25.530us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.360s 14.811us 20 20 100.00
lc_ctrl_csr_aliasing 1.570s 37.281us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 10.130s 80.449us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.690s 770.260us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.320s 14.395us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.170s 146.623us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 19.480s 1915.749us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 16.180s 3024.833us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 19.480s 1915.749us 50 50 100.00
lc_ctrl_prog_failure 4.170s 146.623us 50 50 100.00
lc_ctrl_errors 16.180s 3024.833us 50 50 100.00
lc_ctrl_security_escalation 13.790s 1723.648us 50 50 100.00
lc_ctrl_jtag_state_failure 81.260s 9031.113us 20 20 100.00
lc_ctrl_jtag_prog_failure 12.670s 511.525us 20 20 100.00
lc_ctrl_jtag_errors 104.740s 5179.245us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_csr_hw_reset 3.510s 480.449us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.710s 151.908us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 27.910s 6458.357us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 19.360s 4823.737us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.890s 123.736us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.740s 134.093us 10 10 100.00
lc_ctrl_jtag_alert_test 3.370s 280.075us 10 10 100.00
lc_ctrl_jtag_smoke 14.870s 3021.130us 20 20 100.00
lc_ctrl_jtag_state_post_trans 27.440s 2640.444us 20 20 100.00
lc_ctrl_jtag_prog_failure 12.670s 511.525us 20 20 100.00
lc_ctrl_jtag_errors 104.740s 5179.245us 20 20 100.00
lc_ctrl_jtag_access 21.600s 4515.494us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 34.590s 5486.744us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 26.700s 2766.218us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.590s 79.457us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 403.740s 30563.968us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.780s 39.309us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.130s 574.433us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.130s 574.433us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.310s 69.705us 5 5 100.00
lc_ctrl_csr_rw 1.360s 14.811us 20 20 100.00
lc_ctrl_csr_aliasing 1.570s 37.281us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.220s 92.332us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.310s 69.705us 5 5 100.00
lc_ctrl_csr_rw 1.360s 14.811us 20 20 100.00
lc_ctrl_csr_aliasing 1.570s 37.281us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.220s 92.332us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 4.210s 453.055us 20 20 100.00
lc_ctrl_sec_cm 9.680s 245.774us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.210s 453.055us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.690s 770.260us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 19.480s 1915.749us 50 50 100.00
lc_ctrl_sec_cm 9.680s 245.774us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 19.480s 1915.749us 50 50 100.00
lc_ctrl_sec_cm 9.680s 245.774us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 19.480s 1915.749us 50 50 100.00
lc_ctrl_sec_cm 9.680s 245.774us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 19.480s 1915.749us 50 50 100.00
lc_ctrl_sec_cm 9.680s 245.774us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 19.480s 1915.749us 50 50 100.00
lc_ctrl_sec_cm 9.680s 245.774us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 19.480s 1915.749us 50 50 100.00
lc_ctrl_sec_cm 9.680s 245.774us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 19.480s 1915.749us 50 50 100.00
lc_ctrl_sec_cm 9.680s 245.774us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 19.480s 1915.749us 50 50 100.00
lc_ctrl_sec_cm 9.680s 245.774us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 13.790s 1723.648us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 10.130s 80.449us 50 50 100.00
lc_ctrl_jtag_state_post_trans 27.440s 2640.444us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 17.170s 634.417us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 17.170s 634.417us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 16.650s 1102.838us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 16.990s 1394.029us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 16.990s 1394.029us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 23 50 46.00
lc_ctrl_stress_all_with_rand_reset 133.310s 28700.194us 23 50 46.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 30065529704104417712759119683153840709343079195009982024895020230844363803240 194
UVM_ERROR @ 446905175 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 446905175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75758212670730049682862349300943961327931607994811069364398023353092785335293 6063
UVM_ERROR @ 11500725799 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11500725799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19732114746224729905251327606178864301868090399523996112358518421568258920312 4565
UVM_ERROR @ 1407261941 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1407261941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 20277373856765022059770698307598068944672377546557590767128169226493532563153 3438
UVM_ERROR @ 10541489450 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10541489450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 67133310439894921475071944055557911659262648636460020040817155538705361723888 1673
UVM_ERROR @ 3365681950 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3365681950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14713233830260138222332018028230778547720841504610763722205877971703089772567 10140
UVM_ERROR @ 3582187087 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3582187087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 50556998815012619416485868478439483894881348417670243347078466547695261774671 5798
UVM_ERROR @ 2330558765 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2330558765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 46464522883998545028327532740036653775156117101051919121984863572064199177346 7877
UVM_ERROR @ 14502806331 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14502806331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 8006952044648876317429935563404803147052158519470122382762835547729296554270 3746
UVM_ERROR @ 4271188031 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4271188031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 90546963498324399466693153437602323542831249508819695939685424128999747665688 2119
UVM_ERROR @ 2539401996 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2539401996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 56928009369814298070777629195687526030121887534268352284047452073726304416840 4349
UVM_ERROR @ 1445136169 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1445136169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43808385497938319770572359837262897138405934144470735453579747145118839315266 6177
UVM_ERROR @ 1671280276 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1671280276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64293443552267698826153553950056919878077546339897613714394767216797619761126 162
UVM_ERROR @ 215737635 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 215737635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43096199683317647122964894978368249249726096278006088405570569484466970734369 4660
UVM_ERROR @ 28700193701 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 28700193701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 63275464848285777413484126746330817258378657975720244654336330753722259849563 151
UVM_ERROR @ 628017502 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 628017502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98440262087258426646092886297293144188690935961404937963144788112530996735259 18313
UVM_ERROR @ 14234278192 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14234278192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 87933597926276567943485664406304119856503102768144394142402310323634270331065 1544
UVM_ERROR @ 7840640229 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7840640229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35414580395758790873516430208111112258593786201561588971032574330934974521517 159
UVM_ERROR @ 2348540951 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2348540951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 50990643852750561979209980307946636698232227352096325664520304769540494660523 922
UVM_ERROR @ 1815716429 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1815716429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 57499812533172923590546706748402915663737413574157015365852271914189083189198 3495
UVM_ERROR @ 4842300030 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4842300030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 10093353945268947929526549385134815785835881131468656992769797520264118930537 5691
UVM_ERROR @ 8681161652 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8681161652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93962532438476694667766715274398221517586304105572411528931766124382716029793 8173
UVM_ERROR @ 4007707361 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4007707361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 6582369791535480502409533194951997832798248861863260545485642729561977360309 258
UVM_ERROR @ 4045243676 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4045243676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 53072893984547538394372447361813396322444169908577119113899241101480411352873 2468
UVM_ERROR @ 2225228307 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2225228307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 7305261061698892787246143072176540765031723499248438556997745619305812761243 2079
UVM_ERROR @ 5426222600 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5426222600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 90040925766913485923439052755166613272097295192557141654824422472782975424297 8206
UVM_ERROR @ 8975254308 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 8975254308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60027130241340851632226081675295974633120304332655041925954262606173670961349 5414
UVM_ERROR @ 3838639036 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 3838639036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all 112787515592257530134889921429037587867930758496156956995062262120465434200251 3638
UVM_ERROR @ 9835381447 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 9835381447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---