Simulation Results: lc_ctrl/volatile_unlock_enabled

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.79 %
  • code
  • 89.35 %
  • assert
  • 95.99 %
  • func
  • 96.04 %
  • line
  • 97.87 %
  • branch
  • 96.85 %
  • cond
  • 82.51 %
  • toggle
  • 91.35 %
  • FSM
  • 78.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
48.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 4.280s 106.791us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.400s 42.208us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.400s 60.682us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 1.960s 105.502us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.680s 232.055us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.580s 35.164us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.400s 60.682us 20 20 100.00
lc_ctrl_csr_aliasing 1.680s 232.055us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 11.430s 403.059us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.240s 610.072us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.320s 13.554us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.900s 102.878us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 16.660s 1341.747us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 18.940s 1807.324us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 16.660s 1341.747us 50 50 100.00
lc_ctrl_prog_failure 4.900s 102.878us 50 50 100.00
lc_ctrl_errors 18.940s 1807.324us 50 50 100.00
lc_ctrl_security_escalation 12.050s 1463.740us 50 50 100.00
lc_ctrl_jtag_state_failure 74.620s 13220.463us 20 20 100.00
lc_ctrl_jtag_prog_failure 18.050s 553.870us 20 20 100.00
lc_ctrl_jtag_errors 91.360s 4562.360us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 11.550s 3299.287us 20 20 100.00
lc_ctrl_jtag_state_post_trans 25.210s 4326.149us 20 20 100.00
lc_ctrl_jtag_prog_failure 18.050s 553.870us 20 20 100.00
lc_ctrl_jtag_errors 91.360s 4562.360us 20 20 100.00
lc_ctrl_jtag_access 22.430s 2640.988us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 36.450s 2438.160us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 6.160s 990.273us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.580s 185.142us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 23.860s 5323.005us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 16.860s 6309.347us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.690s 38.178us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.760s 2558.863us 10 10 100.00
lc_ctrl_jtag_alert_test 3.250s 777.106us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 13.290s 2132.451us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.770s 18.951us 50 50 100.00
stress_all 50 50 100.00
lc_ctrl_stress_all 547.540s 86650.370us 50 50 100.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.580s 45.941us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.110s 509.230us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.110s 509.230us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.400s 42.208us 5 5 100.00
lc_ctrl_csr_rw 1.400s 60.682us 20 20 100.00
lc_ctrl_csr_aliasing 1.680s 232.055us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.200s 73.846us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.400s 42.208us 5 5 100.00
lc_ctrl_csr_rw 1.400s 60.682us 20 20 100.00
lc_ctrl_csr_aliasing 1.680s 232.055us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.200s 73.846us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 11.200s 230.186us 5 5 100.00
lc_ctrl_tl_intg_err 3.400s 126.101us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.400s 126.101us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.240s 610.072us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 16.660s 1341.747us 50 50 100.00
lc_ctrl_sec_cm 11.200s 230.186us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 16.660s 1341.747us 50 50 100.00
lc_ctrl_sec_cm 11.200s 230.186us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 16.660s 1341.747us 50 50 100.00
lc_ctrl_sec_cm 11.200s 230.186us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 16.660s 1341.747us 50 50 100.00
lc_ctrl_sec_cm 11.200s 230.186us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 16.660s 1341.747us 50 50 100.00
lc_ctrl_sec_cm 11.200s 230.186us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 16.660s 1341.747us 50 50 100.00
lc_ctrl_sec_cm 11.200s 230.186us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 16.660s 1341.747us 50 50 100.00
lc_ctrl_sec_cm 11.200s 230.186us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 16.660s 1341.747us 50 50 100.00
lc_ctrl_sec_cm 11.200s 230.186us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 12.050s 1463.740us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 11.430s 403.059us 50 50 100.00
lc_ctrl_jtag_state_post_trans 25.210s 4326.149us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.760s 1138.960us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.760s 1138.960us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 13.300s 2855.870us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 15.670s 714.800us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 15.670s 714.800us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 24 50 48.00
lc_ctrl_stress_all_with_rand_reset 155.670s 5343.587us 24 50 48.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 115443972465818503318506958435664088389799967624315882239429520940462016715408 4332
UVM_ERROR @ 12866709224 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12866709224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 94603058904919416946164791407441429432370898214572640204417388269831074374685 2299
UVM_ERROR @ 11045317923 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11045317923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92367559318306482508964202954651299241166644802735503963590071711189186431915 151
UVM_ERROR @ 139269715 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 139269715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 114177394118175863595641342627075096776379852678432011969057269276716717518151 4778
UVM_ERROR @ 2858471626 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2858471626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93705244966293808315298352922863487955981508227019564923438108839213714602290 1562
UVM_ERROR @ 1569252754 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1569252754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 41647225321988953622610508400770925178101397040232557102677064560786438376726 987
UVM_ERROR @ 1791692790 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1791692790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 61230173361186284154350807769814449578780388029210764280292506676383993491414 801
UVM_ERROR @ 434935398 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 434935398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 66634663824059392729220953897143017370076871713819951173929164957228394328103 2030
UVM_ERROR @ 2261003915 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2261003915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16466577876478625639187062238438226220288500118803333754356488706089472648106 2806
UVM_ERROR @ 2166523036 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2166523036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43264774047753842772782227181760329829048063884705951286247483655727648384453 2172
UVM_ERROR @ 2147406093 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2147406093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 40480428145545294905894715940810900844105224800522499321768508712736950174789 5551
UVM_ERROR @ 1203693122 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1203693122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16950417345796012323347531628766232622841312720627391147004771493528171318742 150
UVM_ERROR @ 455343821 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 455343821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 77485803724169582480325988752660730357581972314796043555250187708200766036830 6533
UVM_ERROR @ 1221537865 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1221537865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92062950997614258353634650294526679679316867359493100968886747897042530763991 7051
UVM_ERROR @ 32566484251 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 32566484251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93754425956229862062192955942717009469029730932981787401802974408952465062306 3404
UVM_ERROR @ 6726224499 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6726224499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 49155695578495152367849087010044604140872560037419576357504778083455162059834 254
UVM_ERROR @ 934051467 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 934051467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 41771976688459928705186593261355753691864418326208166647577210962879559134138 6600
UVM_ERROR @ 9199350906 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9199350906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93690125361157615197551001792818210026257406404515105807320891315285906748459 7608
UVM_ERROR @ 3727956098 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3727956098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 82210306441932925912988258417070180421329014967623249106750107317643708073974 150
UVM_ERROR @ 422265978 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 422265978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 86670124398519371873488192437672002435750217252806280208507765915669354911540 962
UVM_ERROR @ 25438784869 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 25438784869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91495623744482041891964830723382564907382973354259256587183653105309158466504 2009
UVM_ERROR @ 8844057676 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8844057676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 48067706581395828208520597185611178486404070067979324473206346608826307007427 933
UVM_ERROR @ 1981840300 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1981840300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 45142463480623351701500816589414351186022439723624519368613219290373722353099 273
UVM_ERROR @ 566273172 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 566273172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96102882359794984448265408197069036759007770211089774539235453814764887343539 2393
UVM_ERROR @ 9838844499 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9838844499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 80221739763241939442224069873983648132543976670343814044157098075382584523201 3178
UVM_ERROR @ 2269929620 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2269929620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 61393411007759668794408589598073011064263396845602705623896248883601447954643 3270
UVM_ERROR @ 8070502344 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 8070502344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---