Simulation Results: otbn

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.91 %
  • code
  • 96.79 %
  • assert
  • 96.95 %
  • func
  • 100.00 %
  • block
  • 99.50 %
  • line
  • 99.66 %
  • branch
  • 93.72 %
  • toggle
  • 93.78 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.91%
V2S
98.82%
V3
50.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 171.167us 1 1 100.00
single_binary 100 100 100.00
otbn_single 1270.000s 3955.504us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 17.000s 41.938us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 9.000s 12.509us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 13.000s 95.343us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 9.000s 29.683us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 14.000s 111.964us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 9.000s 12.509us 20 20 100.00
otbn_csr_aliasing 9.000s 29.683us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 125.000s 3955.382us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 71.000s 1253.323us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 54.000s 112.932us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 193.000s 600.254us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 123.000s 288.850us 9 10 90.00
stress_all 9 10 90.00
otbn_stress_all 108.000s 830.279us 9 10 90.00
lc_escalation 59 60 98.33
otbn_escalate 135.000s 428.264us 59 60 98.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 10.000s 74.306us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 59.000s 449.767us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 6.000s 26.527us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 9.000s 30.464us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 14.000s 275.924us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 14.000s 275.924us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 17.000s 41.938us 5 5 100.00
otbn_csr_rw 9.000s 12.509us 20 20 100.00
otbn_csr_aliasing 9.000s 29.683us 5 5 100.00
otbn_same_csr_outstanding 10.000s 17.399us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 17.000s 41.938us 5 5 100.00
otbn_csr_rw 9.000s 12.509us 20 20 100.00
otbn_csr_aliasing 9.000s 29.683us 5 5 100.00
otbn_same_csr_outstanding 10.000s 17.399us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 13.000s 34.904us 10 10 100.00
otbn_dmem_err 30.000s 160.584us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 12.000s 229.585us 5 5 100.00
otbn_controller_ispr_rdata_err 10.000s 61.389us 5 5 100.00
otbn_mac_bignum_acc_err 11.000s 60.244us 5 5 100.00
otbn_urnd_err 6.000s 17.127us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 10.000s 33.799us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 6.000s 41.979us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 8.000s 19.988us 10 10 100.00
tl_intg_err 25 25 100.00
otbn_tl_intg_err 78.000s 390.547us 20 20 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
passthru_mem_tl_intg_err 18 20 90.00
otbn_passthru_mem_tl_intg_err 63.000s 452.520us 18 20 90.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 171.167us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 30.000s 160.584us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 13.000s 34.904us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 78.000s 390.547us 20 20 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 135.000s 428.264us 59 60 98.33
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 13.000s 34.904us 10 10 100.00
otbn_dmem_err 30.000s 160.584us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 74.306us 5 5 100.00
otbn_illegal_mem_acc 10.000s 33.799us 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 1270.000s 3955.504us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 13.000s 34.904us 10 10 100.00
otbn_dmem_err 30.000s 160.584us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 74.306us 5 5 100.00
otbn_illegal_mem_acc 10.000s 33.799us 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 135.000s 428.264us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 13.000s 34.904us 10 10 100.00
otbn_dmem_err 30.000s 160.584us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 74.306us 5 5 100.00
otbn_illegal_mem_acc 10.000s 33.799us 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 1270.000s 3955.504us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 14.000s 49.657us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 10.000s 125.685us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 147.000s 1302.495us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 147.000s 1302.495us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 12.000s 19.762us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 15.000s 82.673us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 32.000s 361.749us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 32.000s 361.749us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 17.000s 36.714us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 1270.000s 3955.504us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 1270.000s 3955.504us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 1270.000s 3955.504us 100 100 100.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 123.000s 288.850us 9 10 90.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 1270.000s 3955.504us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 1270.000s 3955.504us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 22.000s 146.056us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 1270.000s 3955.504us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 266.000s 2212.484us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
otbn_stress_all_with_rand_reset 328.000s 1510.531us 5 10 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 68.161us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 74930005218673870431696330712999471955381728406808240309531302866401309548724 86
UVM_FATAL @ 1468223 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1468223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 105031551165999847910718441646560863219486439045786185032113811444166786696915 101
UVM_FATAL @ 32688633 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 32688633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 89246056596936524076817094782415676729585418225131450919584470901560436884227 392
UVM_ERROR @ 3771378371 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3771378371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 90825994878772129967010745222154227006341556382101467511351557377549005443807 198
UVM_ERROR @ 1058657376 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1058657376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 108879537600693652769683205577609795106595812523377504808880486192965385124388 337
UVM_ERROR @ 580896914 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 580896914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 35961420506598782467728173916840720886791453606514935432562653454133574251862 234
UVM_FATAL @ 182262216 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 182262216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_rnd_if.sv,175): Assertion EdgePREFETCHINGToFULL_A has failed (* cycles, starting * PS)
otbn_multi 77588947463682686464558447974156368821593489766499683743268042692996347266520 154
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_rnd_if.sv,175): (time 91759518 PS) Assertion tb.dut.u_otbn_core.u_otbn_rnd.i_otbn_rnd_if.EdgePREFETCHINGToFULL_A has failed (2 cycles, starting 91749314 PS)
UVM_ERROR @ 91759518 ps: (otbn_rnd_if.sv:175) [ASSERT FAILED] EdgePREFETCHINGToFULL_A
UVM_INFO @ 91759518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
otbn_stress_all 12115511705969259653971983261165046810917837775243693768868760602724027944854 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
otbn_stress_all_with_rand_reset 109798810988383401661080639156639368202044178504700974185057581734569163343885 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_escalate 929523373101844166646190209942954355059375065488789135276658977779710067678 107
UVM_ERROR @ 3177113 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 3177113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---