Simulation Results: rom_ctrl/32kb

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.64 %
  • code
  • 99.68 %
  • assert
  • 96.95 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.20%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.000s 528.077us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 6.760s 405.895us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 5.650s 123.843us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 6.890s 2182.033us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 5.050s 385.432us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.370s 178.833us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 5.650s 123.843us 20 20 100.00
rom_ctrl_csr_aliasing 5.050s 385.432us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 6.270s 1027.383us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 6.560s 169.706us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 7.340s 537.961us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 23.530s 2141.890us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 10.710s 1595.717us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 6.580s 168.049us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 10.220s 1742.377us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 10.220s 1742.377us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 6.760s 405.895us 5 5 100.00
rom_ctrl_csr_rw 5.650s 123.843us 20 20 100.00
rom_ctrl_csr_aliasing 5.050s 385.432us 5 5 100.00
rom_ctrl_same_csr_outstanding 6.760s 1450.947us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 6.760s 405.895us 5 5 100.00
rom_ctrl_csr_rw 5.650s 123.843us 20 20 100.00
rom_ctrl_csr_aliasing 5.050s 385.432us 5 5 100.00
rom_ctrl_same_csr_outstanding 6.760s 1450.947us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 97.690s 4946.059us 16 20 80.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.950s 3161.732us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 245.100s 475.615us 5 5 100.00
rom_ctrl_tl_intg_err 57.670s 1077.465us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 245.100s 475.615us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 245.100s 475.615us 5 5 100.00
sec_cm_checker_ctr_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 97.690s 4946.059us 16 20 80.00
sec_cm_checker_ctrl_flow_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 97.690s 4946.059us 16 20 80.00
sec_cm_checker_fsm_local_esc 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 97.690s 4946.059us 16 20 80.00
sec_cm_compare_ctrl_flow_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 97.690s 4946.059us 16 20 80.00
sec_cm_compare_ctr_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 97.690s 4946.059us 16 20 80.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 245.100s 475.615us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 245.100s 475.615us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.000s 528.077us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.000s 528.077us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.000s 528.077us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 57.670s 1077.465us 20 20 100.00
sec_cm_bus_local_esc 18 22 81.82
rom_ctrl_corrupt_sig_fatal_chk 97.690s 4946.059us 16 20 80.00
rom_ctrl_kmac_err_chk 10.710s 1595.717us 2 2 100.00
sec_cm_mux_mubi 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 97.690s 4946.059us 16 20 80.00
sec_cm_mux_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 97.690s 4946.059us 16 20 80.00
sec_cm_ctrl_redun 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 97.690s 4946.059us 16 20 80.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.950s 3161.732us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 245.100s 475.615us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 432.170s 18890.540us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 80562859400908724642769597053413179381724593370530686356681284429976932101267 89
UVM_ERROR @ 1206059573 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1206059573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 100412106333182509213504446614028992355683008879461047115812538579241793718673 107
UVM_ERROR @ 7252862599 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 7252862599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 114044191897864331712577034897426152538140161093875069716049345646940121408501 78
UVM_ERROR @ 365673754 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 365673754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 36735393636330596569027424366552180366240919581167282728626463466676398886205 82
UVM_ERROR @ 601899011 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 601899011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---