| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 12.460s | 340.529us | 2 | 2 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 17.230s | 395.301us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rom_ctrl_csr_rw | 11.570s | 4155.327us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_bit_bash | 9.120s | 698.730us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_aliasing | 10.110s | 313.406us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 15.070s | 7154.532us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rom_ctrl_csr_rw | 11.570s | 4155.327us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 10.110s | 313.406us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| rom_ctrl_mem_walk | 11.110s | 289.112us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| rom_ctrl_mem_partial_access | 10.180s | 289.815us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_max_throughput_chk | 10.870s | 227.660us | 2 | 2 | 100.00 | |
| stress_all | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all | 46.020s | 19821.453us | 20 | 20 | 100.00 | |
| kmac_err_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_kmac_err_chk | 19.260s | 563.973us | 2 | 2 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rom_ctrl_alert_test | 14.080s | 1022.003us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_errors | 16.030s | 291.370us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_errors | 16.030s | 291.370us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 17.230s | 395.301us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_rw | 11.570s | 4155.327us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 10.110s | 313.406us | 5 | 5 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 12.530s | 315.402us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 17.230s | 395.301us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_rw | 11.570s | 4155.327us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 10.110s | 313.406us | 5 | 5 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 12.530s | 315.402us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 281.130s | 33389.767us | 20 | 20 | 100.00 | |
| passthru_mem_tl_intg_err | 20 | 20 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 52.330s | 2122.643us | 20 | 20 | 100.00 | |
| tl_intg_err | 25 | 25 | 100.00 | |||
| rom_ctrl_tl_intg_err | 136.050s | 2743.998us | 20 | 20 | 100.00 | |
| rom_ctrl_sec_cm | 467.820s | 2131.434us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 467.820s | 2131.434us | 5 | 5 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 467.820s | 2131.434us | 5 | 5 | 100.00 | |
| sec_cm_checker_ctr_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 281.130s | 33389.767us | 20 | 20 | 100.00 | |
| sec_cm_checker_ctrl_flow_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 281.130s | 33389.767us | 20 | 20 | 100.00 | |
| sec_cm_checker_fsm_local_esc | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 281.130s | 33389.767us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctrl_flow_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 281.130s | 33389.767us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctr_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 281.130s | 33389.767us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctr_redun | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 467.820s | 2131.434us | 5 | 5 | 100.00 | |
| sec_cm_fsm_sparse | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 467.820s | 2131.434us | 5 | 5 | 100.00 | |
| sec_cm_mem_scramble | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 12.460s | 340.529us | 2 | 2 | 100.00 | |
| sec_cm_mem_digest | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 12.460s | 340.529us | 2 | 2 | 100.00 | |
| sec_cm_intersig_mubi | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 12.460s | 340.529us | 2 | 2 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_intg_err | 136.050s | 2743.998us | 20 | 20 | 100.00 | |
| sec_cm_bus_local_esc | 22 | 22 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 281.130s | 33389.767us | 20 | 20 | 100.00 | |
| rom_ctrl_kmac_err_chk | 19.260s | 563.973us | 2 | 2 | 100.00 | |
| sec_cm_mux_mubi | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 281.130s | 33389.767us | 20 | 20 | 100.00 | |
| sec_cm_mux_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 281.130s | 33389.767us | 20 | 20 | 100.00 | |
| sec_cm_ctrl_redun | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 281.130s | 33389.767us | 20 | 20 | 100.00 | |
| sec_cm_ctrl_mem_integrity | 20 | 20 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 52.330s | 2122.643us | 20 | 20 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 467.820s | 2131.434us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 366.330s | 4976.969us | 20 | 20 | 100.00 | |