Simulation Results: rstmgr

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.56 %
  • code
  • 99.59 %
  • assert
  • 97.62 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.380s 58.152us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.060s 93.346us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 0.920s 36.746us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 3.520s 143.224us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.330s 55.328us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.510s 97.575us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 0.920s 36.746us 20 20 100.00
rstmgr_csr_aliasing 1.330s 55.328us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.830s 221.899us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 1.160s 37.742us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.260s 97.645us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 5.840s 910.888us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 5.840s 910.888us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 5.840s 910.888us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 5.840s 910.888us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 43.930s 5844.684us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.590s 153.760us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 2.550s 90.582us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 2.550s 90.582us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.060s 93.346us 5 5 100.00
rstmgr_csr_rw 0.920s 36.746us 20 20 100.00
rstmgr_csr_aliasing 1.330s 55.328us 5 5 100.00
rstmgr_same_csr_outstanding 1.200s 48.347us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.060s 93.346us 5 5 100.00
rstmgr_csr_rw 0.920s 36.746us 20 20 100.00
rstmgr_csr_aliasing 1.330s 55.328us 5 5 100.00
rstmgr_same_csr_outstanding 1.200s 48.347us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 33.490s 7430.675us 5 5 100.00
rstmgr_tl_intg_err 5.040s 774.580us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 33.490s 7430.675us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 33.490s 7430.675us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 5.040s 774.580us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.300s 66.873us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 3.960s 469.637us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 2.410s 290.969us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 33.490s 7430.675us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 0.920s 36.746us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 0.920s 36.746us 20 20 100.00