Simulation Results

Simulation Results: spi_host

20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.82 %

code
95.06 %

assert
95.64 %

func
90.76 %

block
97.00 %

line
98.76 %

branch
93.45 %

toggle
88.02 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.74%
V2S		100.00%
unmapped		100.00%

115/115 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_host_smoke	70.000s	7915.555us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_host_csr_hw_reset	2.000s	29.920us	5	5	100.00
csr_rw				20	20	100.00
	spi_host_csr_rw	2.000s	23.862us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_host_csr_bit_bash	3.000s	531.990us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_host_csr_aliasing	2.000s	32.277us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_host_csr_mem_rw_with_rand_reset	2.000s	115.173us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_host_csr_rw	2.000s	23.862us	20	20	100.00
	spi_host_csr_aliasing	2.000s	32.277us	5	5	100.00
mem_walk				5	5	100.00
	spi_host_mem_walk	2.000s	15.329us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_host_mem_partial_access	2.000s	21.277us	5	5	100.00

768/770 passed

99.74 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
performance				50	50	100.00
	spi_host_performance	34.000s	38.388us	50	50	100.00
error_event_intr				150	150	100.00
	spi_host_overflow_underflow	38.000s	803.856us	50	50	100.00
	spi_host_error_cmd	34.000s	18.254us	50	50	100.00
	spi_host_event	742.000s	56950.487us	50	50	100.00
clock_rate				49	50	98.00
	spi_host_speed	36.000s	236.493us	49	50	98.00
speed				49	50	98.00
	spi_host_speed	36.000s	236.493us	49	50	98.00
chip_select_timing				49	50	98.00
	spi_host_speed	36.000s	236.493us	49	50	98.00
sw_reset				50	50	100.00
	spi_host_sw_reset	163.000s	4711.929us	50	50	100.00
passthrough_mode				50	50	100.00
	spi_host_passthrough_mode	34.000s	22.911us	50	50	100.00
cpol_cpha				49	50	98.00
	spi_host_speed	36.000s	236.493us	49	50	98.00
full_cycle				49	50	98.00
	spi_host_speed	36.000s	236.493us	49	50	98.00
duplex				50	50	100.00
	spi_host_smoke	70.000s	7915.555us	50	50	100.00
tx_rx_only				50	50	100.00
	spi_host_smoke	70.000s	7915.555us	50	50	100.00
stress_all				50	50	100.00
	spi_host_stress_all	141.000s	11389.169us	50	50	100.00
spien				50	50	100.00
	spi_host_spien	242.000s	43294.650us	50	50	100.00
stall				49	50	98.00
	spi_host_status_stall	1534.000s	45062.783us	49	50	98.00
Idlecsbactive				50	50	100.00
	spi_host_idlecsbactive	42.000s	9799.432us	50	50	100.00
data_fifo_status				50	50	100.00
	spi_host_overflow_underflow	38.000s	803.856us	50	50	100.00
alert_test				50	50	100.00
	spi_host_alert_test	34.000s	55.768us	50	50	100.00
intr_test				50	50	100.00
	spi_host_intr_test	2.000s	21.796us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_host_tl_errors	3.000s	1075.925us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_host_tl_errors	3.000s	1075.925us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	29.920us	5	5	100.00
	spi_host_csr_rw	2.000s	23.862us	20	20	100.00
	spi_host_csr_aliasing	2.000s	32.277us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	29.983us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	29.920us	5	5	100.00
	spi_host_csr_rw	2.000s	23.862us	20	20	100.00
	spi_host_csr_aliasing	2.000s	32.277us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	29.983us	20	20	100.00

V2S

25/25 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_host_sec_cm	34.000s	135.785us	5	5	100.00
	spi_host_tl_intg_err	2.000s	347.624us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_host_tl_intg_err	2.000s	347.624us	20	20	100.00

unmapped

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				10	10	100.00
	spi_host_upper_range_clkdiv	630.000s	17243.854us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = ns spi_host_reg_block.status.rxqd (addr=, Comparison=CompareOpEq, exp_data=, call_count=
	spi_host_speed	65169985867255072904867033660587599781626348484611141087231058985636692212071	281	UVM_FATAL @ 10051069945 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xa9e03354, Comparison=CompareOpEq, exp_data=0x0, call_count=44 UVM_INFO @ 10051069945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed
	spi_host_status_stall	109526881893170224358050247889478628794655438700649761741121430898014607863287	8149	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 25916360943 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed UVM_ERROR @ 25916360943 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=25916361000 ps UVM_INFO @ 25916360943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---