Simulation Results: sram_ctrl/ret

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.17 %
  • code
  • 83.49 %
  • assert
  • 96.43 %
  • func
  • 96.60 %
  • block
  • 94.01 %
  • line
  • 95.19 %
  • branch
  • 89.83 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
98.57%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 27.000s 212.973us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 17.095us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 22.261us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 4.000s 706.684us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 40.804us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 50.545us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 22.261us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 40.804us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 12.000s 467.773us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 7.000s 94.174us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 47.000s 1064.221us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 265.000s 28645.716us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 32.000s 464.163us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 18.000s 640.171us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 19.000s 326.743us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 18.000s 1061.755us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 26.000s 54.369us 5 5 100.00
sram_ctrl_partial_access_b2b 417.000s 22078.202us 5 5 100.00
max_throughput 5 15 33.33
sram_ctrl_max_throughput 25.000s 44.396us 0 5 0.00
sram_ctrl_throughput_w_partial_write 24.000s 170.130us 5 5 100.00
sram_ctrl_throughput_w_readback 23.000s 102.093us 0 5 0.00
regwen 5 5 100.00
sram_ctrl_regwen 14.000s 664.853us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 78.173us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 57.000s 2750.116us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 33.985us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.000s 118.418us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.000s 118.418us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 17.095us 5 5 100.00
sram_ctrl_csr_rw 2.000s 22.261us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 40.804us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 22.348us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 17.095us 5 5 100.00
sram_ctrl_csr_rw 2.000s 22.261us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 40.804us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 22.348us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 7.000s 7733.420us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 5.000s 1394.732us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 501.455us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 1394.732us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 501.455us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 14.000s 664.853us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 14.000s 664.853us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 22.261us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 18.000s 1061.755us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 18.000s 1061.755us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 18.000s 1061.755us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 19.000s 326.743us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 132.883us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 7.000s 7733.420us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 2.000s 79.181us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 27.000s 212.973us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 27.000s 212.973us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 18.000s 1061.755us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 1394.732us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 19.000s 326.743us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 1394.732us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1394.732us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 27.000s 212.973us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1394.732us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 84.000s 5596.201us 5 5 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 20799860805050529012881587239419909694264986772090841804888235844829419339476 102
UVM_FATAL @ 44395700 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 44395700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 98292853251294411696080087891759226237917664633413391379511947603733681288432 102
UVM_FATAL @ 102093441 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 102093441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 52616475047636773692541306729702409842803239967624758715804392096691966522011 102
UVM_FATAL @ 22216018 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 22216018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 28148081872589080389330808357282621916626982902341279303071145291755691228973 102
UVM_FATAL @ 35972230 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 35972230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 57118097735091415761566600048744915547861088150324730461533483511759664913777 102
UVM_FATAL @ 94691195 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 94691195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 8906530043116117876669327982647804642967049457199534206825806615436162177673 102
UVM_FATAL @ 311053354 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 311053354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 87703573786063596465588543944018745448534883241031729844465120573719077898875 102
UVM_FATAL @ 169437527 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 169437527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 32212666857381637893870860951684307699006653186478995391115177281324960150749 102
UVM_FATAL @ 125524091 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 125524091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 60966078962880688042780627484736463105385629819050351672774003774405677339427 102
UVM_FATAL @ 25410753 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 25410753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 79453406376131284317531453863305798818694114288926827380879346742800925653198 102
UVM_FATAL @ 41046431 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 41046431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 110308674451763587850313495700052809866601604158125654681029758861822105384490 88
UVM_ERROR @ 331160493 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 331160493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---