Simulation Results

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
xbar_smoke				50	50	100.00
	xbar_smoke	22.000s	3092.611us	50	50	100.00

838/850 passed

98.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
xbar_base_random_sequence				50	50	100.00
	xbar_random	219.420s	7887.272us	50	50	100.00
xbar_random_delay				298	300	99.33
	xbar_smoke_zero_delays	8.240s	49.440us	50	50	100.00
	xbar_smoke_large_delays	360.910s	53261.645us	50	50	100.00
	xbar_smoke_slow_rsp	475.690s	105385.754us	50	50	100.00
	xbar_random_zero_delays	90.820s	805.050us	50	50	100.00
	xbar_random_large_delays	1916.450s	239989.373us	49	50	98.00
	xbar_random_slow_rsp	2493.930s	299334.776us	49	50	98.00
xbar_unmapped_address				100	100	100.00
	xbar_unmapped_addr	136.100s	9027.404us	50	50	100.00
	xbar_error_and_unmapped_addr	118.120s	10690.861us	50	50	100.00
xbar_error_cases				100	100	100.00
	xbar_error_random	217.610s	6347.402us	50	50	100.00
	xbar_error_and_unmapped_addr	118.120s	10690.861us	50	50	100.00
xbar_all_access_same_device				90	100	90.00
	xbar_access_same_device	410.510s	8633.674us	50	50	100.00
	xbar_access_same_device_slow_rsp	3539.220s	600000.000us	40	50	80.00
xbar_all_hosts_use_same_source_id				50	50	100.00
	xbar_same_source	200.320s	16306.044us	50	50	100.00
xbar_stress_all				100	100	100.00
	xbar_stress_all	1662.680s	219611.474us	50	50	100.00
	xbar_stress_all_with_error	1555.930s	188095.396us	50	50	100.00
xbar_stress_with_reset				100	100	100.00
	xbar_stress_all_with_rand_reset	1464.390s	3425.721us	50	50	100.00
	xbar_stress_all_with_reset_error	1445.270s	5251.139us	50	50	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	xbar_access_same_device_slow_rsp	40076791356294985602829628177864730360765568048184362815047645287219541163372	119	UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	xbar_access_same_device_slow_rsp	27982185178025000971251914142612215413496195586308051634590101161061741758819	194	UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	xbar_access_same_device_slow_rsp	18522505936800202493463693377081139860217772684007796097197960818950445851871	183	UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	xbar_access_same_device_slow_rsp	29845180629189327984889770097284258227718005683182867580330692544624117000754	153	UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	xbar_random_slow_rsp	5300340289619127591152225853837190781192017176489167927274079236800429945379	135	UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	xbar_access_same_device_slow_rsp	30770115659114073180948398530753076306236652006771560452521910502438864454766	122	UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	xbar_access_same_device_slow_rsp	42946309928386287973046551920257872300706475944249791624378497202749980552843	122	UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	xbar_access_same_device_slow_rsp	42853634891913217516250275183868046625359266951401736660253175233314043489347	122	UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	xbar_random_large_delays	60167973033254898386056024597086118593775530904070747128478893600683937214254	165	UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	xbar_access_same_device_slow_rsp	112951429837565277678410856625201464162291954017623964205667329642850979230484	107	UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	xbar_access_same_device_slow_rsp	70620242168363252781190228606623308580527556808888995533073867934701271639187	154	UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	xbar_access_same_device_slow_rsp	1763989954061121249759778677127190197530156203918898719691505604253727468249	None	Job timed out after 60 minutes

V1		100.00%
V2		98.59%

Simulation Results: xbar_main

Error Messages