Simulation Results: ac_range_check

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
97.89%
V2
97.93%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 18 20 90.00
ac_range_check_smoke 92.000s 2866.959us 18 20 90.00
ac_range_check_smoke_racl 20 20 100.00
ac_range_check_smoke_racl 96.000s 6921.291us 20 20 100.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 3.000s 33.636us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 4.000s 139.829us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 55.000s 12272.808us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 33.000s 1052.098us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 88.452us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 4.000s 139.829us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 1052.098us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 37.000s 145.444us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 79.000s 1131.696us 1 1 100.00
stress_all 45 50 90.00
ac_range_check_stress_all 313.000s 52994.917us 45 50 90.00
alert_test 50 50 100.00
ac_range_check_alert_test 35.000s 15.385us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 2.000s 15.671us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 7.000s 145.643us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 7.000s 145.643us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 33.636us 5 5 100.00
ac_range_check_csr_rw 4.000s 139.829us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 1052.098us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 143.751us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 33.636us 5 5 100.00
ac_range_check_csr_rw 4.000s 139.829us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 1052.098us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 143.751us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 27.000s 988.852us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 27.000s 988.852us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 27.000s 988.852us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 27.000s 988.852us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 120.000s 8859.029us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 35.000s 32.421us 5 5 100.00
ac_range_check_tl_intg_err 16.000s 1605.683us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 464.000s 24888.180us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 68.000s 992.516us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_smoke 25150095720920798805871029496668705931385848799530834202895432959145723827023 4476
UVM_ERROR @ 2431962288 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2431962288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 59248039408785054159181661064219063990731586817374465299472252634149389564761 4618
UVM_ERROR @ 1395531906 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1395531906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 93636945689739794445877817007298145980226362039003529036880134340115284206745 4597
UVM_ERROR @ 6018940987 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 6018940987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 106652734777267196511902600768402677045341671615763607137371999611966752806515 4563
UVM_ERROR @ 670517940 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 670517940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 60146638765414851977058642185410569501234964051143147594394194481312318577539 12775
UVM_ERROR @ 6531396318 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 6531396318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 39714955368724418004787532149370176771352267246513082093452225439374719215994 22377
UVM_ERROR @ 8474306196 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 8474306196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_predictor.sv:163) [predict] Unable to get any item from tl_filt_d_chan_fifo.
ac_range_check_stress_all 107877457622629782476060821539790872238701102172905907638457033580715758233450 12333
UVM_ERROR @ 100487930942 ps: (ac_range_check_predictor.sv:163) [uvm_test_top.env.scoreboard.predict] Unable to get any item from tl_filt_d_chan_fifo.
UVM_INFO @ 100487930942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---