Simulation Results: hmac

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.04 %
  • code
  • 99.33 %
  • assert
  • 97.80 %
  • func
  • 100.00 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.91 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 14.780s 3267.020us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.270s 121.528us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.330s 31.496us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 15.420s 1223.919us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 8.680s 688.600us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 667.160s 189942.274us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.330s 31.496us 20 20 100.00
hmac_csr_aliasing 8.680s 688.600us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 108.300s 11804.706us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 103.170s 22871.554us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 298.650s 12657.997us 30 30 100.00
hmac_test_sha384_vectors 577.080s 13113.893us 75 75 100.00
hmac_test_sha512_vectors 522.830s 54958.469us 75 75 100.00
hmac_test_hmac256_vectors 14.990s 473.966us 50 50 100.00
hmac_test_hmac384_vectors 16.990s 342.822us 60 60 100.00
hmac_test_hmac512_vectors 21.110s 460.016us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 33.390s 647.783us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1175.840s 6236.432us 10 10 100.00
error 10 10 100.00
hmac_error 130.400s 28337.513us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 167.920s 25334.402us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 14.780s 3267.020us 10 10 100.00
hmac_long_msg 108.300s 11804.706us 10 10 100.00
hmac_back_pressure 103.170s 22871.554us 25 25 100.00
hmac_datapath_stress 1175.840s 6236.432us 10 10 100.00
hmac_burst_wr 33.390s 647.783us 50 50 100.00
hmac_stress_all 2097.020s 53497.037us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 14.780s 3267.020us 10 10 100.00
hmac_long_msg 108.300s 11804.706us 10 10 100.00
hmac_back_pressure 103.170s 22871.554us 25 25 100.00
hmac_datapath_stress 1175.840s 6236.432us 10 10 100.00
hmac_wipe_secret 167.920s 25334.402us 10 10 100.00
hmac_test_sha256_vectors 298.650s 12657.997us 30 30 100.00
hmac_test_sha384_vectors 577.080s 13113.893us 75 75 100.00
hmac_test_sha512_vectors 522.830s 54958.469us 75 75 100.00
hmac_test_hmac256_vectors 14.990s 473.966us 50 50 100.00
hmac_test_hmac384_vectors 16.990s 342.822us 60 60 100.00
hmac_test_hmac512_vectors 21.110s 460.016us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 14.780s 3267.020us 10 10 100.00
hmac_long_msg 108.300s 11804.706us 10 10 100.00
hmac_back_pressure 103.170s 22871.554us 25 25 100.00
hmac_datapath_stress 1175.840s 6236.432us 10 10 100.00
hmac_burst_wr 33.390s 647.783us 50 50 100.00
hmac_error 130.400s 28337.513us 10 10 100.00
hmac_wipe_secret 167.920s 25334.402us 10 10 100.00
hmac_test_sha256_vectors 298.650s 12657.997us 30 30 100.00
hmac_test_sha384_vectors 577.080s 13113.893us 75 75 100.00
hmac_test_sha512_vectors 522.830s 54958.469us 75 75 100.00
hmac_test_hmac256_vectors 14.990s 473.966us 50 50 100.00
hmac_test_hmac384_vectors 16.990s 342.822us 60 60 100.00
hmac_test_hmac512_vectors 21.110s 460.016us 75 75 100.00
hmac_stress_all 2097.020s 53497.037us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2097.020s 53497.037us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.950s 15.340us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.970s 14.086us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.430s 1656.362us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.430s 1656.362us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.270s 121.528us 5 5 100.00
hmac_csr_rw 1.330s 31.496us 20 20 100.00
hmac_csr_aliasing 8.680s 688.600us 5 5 100.00
hmac_same_csr_outstanding 2.830s 121.016us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.270s 121.528us 5 5 100.00
hmac_csr_rw 1.330s 31.496us 20 20 100.00
hmac_csr_aliasing 8.680s 688.600us 5 5 100.00
hmac_same_csr_outstanding 2.830s 121.016us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_tl_intg_err 5.220s 278.765us 20 20 100.00
hmac_sec_cm 1.490s 96.875us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 5.220s 278.765us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 14.780s 3267.020us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.660s 157.530us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 516.210s 34162.026us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.810s 486.673us 1 1 100.00