Simulation Results

Simulation Results: keymgr_dpe

24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
66.36 %

code
84.22 %

assert
97.64 %

func
17.22 %

line
97.67 %

branch
94.50 %

cond
90.08 %

toggle
63.15 %

FSM
75.68 %

Validation stages

V1		100.00%
V2		100.00%
V2S		100.00%

V1

105/105 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	keymgr_dpe_smoke	377.030s	40269.377us	50	50	100.00
csr_hw_reset				5	5	100.00
	keymgr_dpe_csr_hw_reset	1.410s	66.729us	5	5	100.00
csr_rw				20	20	100.00
	keymgr_dpe_csr_rw	1.440s	24.746us	20	20	100.00
csr_bit_bash				5	5	100.00
	keymgr_dpe_csr_bit_bash	9.420s	777.191us	5	5	100.00
csr_aliasing				5	5	100.00
	keymgr_dpe_csr_aliasing	7.850s	4506.782us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	keymgr_dpe_csr_mem_rw_with_rand_reset	1.860s	37.822us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	keymgr_dpe_csr_rw	1.440s	24.746us	20	20	100.00
	keymgr_dpe_csr_aliasing	7.850s	4506.782us	5	5	100.00

V2

170/170 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
intr_test				50	50	100.00
	keymgr_dpe_intr_test	1.070s	24.003us	50	50	100.00
alert_test				50	50	100.00
	keymgr_dpe_alert_test	1.410s	138.832us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	keymgr_dpe_tl_errors	3.910s	327.180us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	keymgr_dpe_tl_errors	3.910s	327.180us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	keymgr_dpe_csr_hw_reset	1.410s	66.729us	5	5	100.00
	keymgr_dpe_csr_rw	1.440s	24.746us	20	20	100.00
	keymgr_dpe_csr_aliasing	7.850s	4506.782us	5	5	100.00
	keymgr_dpe_same_csr_outstanding	3.180s	195.003us	20	20	100.00
tl_d_partial_access				50	50	100.00
	keymgr_dpe_csr_hw_reset	1.410s	66.729us	5	5	100.00
	keymgr_dpe_csr_rw	1.440s	24.746us	20	20	100.00
	keymgr_dpe_csr_aliasing	7.850s	4506.782us	5	5	100.00
	keymgr_dpe_same_csr_outstanding	3.180s	195.003us	20	20	100.00

V2S

65/65 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	keymgr_dpe_tl_intg_err	6.000s	410.783us	20	20	100.00
	keymgr_dpe_sec_cm	26.060s	1338.862us	5	5	100.00
shadow_reg_update_error				20	20	100.00
	keymgr_dpe_shadow_reg_errors	3.250s	167.883us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	keymgr_dpe_shadow_reg_errors	3.250s	167.883us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	keymgr_dpe_shadow_reg_errors	3.250s	167.883us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	keymgr_dpe_shadow_reg_errors	3.250s	167.883us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	keymgr_dpe_shadow_reg_errors_with_csr_rw	7.870s	902.296us	20	20	100.00
prim_count_check				5	5	100.00
	keymgr_dpe_sec_cm	26.060s	1338.862us	5	5	100.00
prim_fsm_check				5	5	100.00
	keymgr_dpe_sec_cm	26.060s	1338.862us	5	5	100.00