Simulation Results: kmac/masked

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.64 %
  • code
  • 93.94 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.18 %
  • branch
  • 97.01 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 78.87 %
Validation stages
V1
100.00%
V2
99.87%
V2S
99.56%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 71.190s 5124.958us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.250s 141.582us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.340s 42.580us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 15.520s 5991.281us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.360s 533.807us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.690s 174.506us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.340s 42.580us 20 20 100.00
kmac_csr_aliasing 6.360s 533.807us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.090s 39.196us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 2.080s 167.516us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3465.100s 133601.875us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1253.010s 65102.643us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2150.470s 63645.279us 5 5 100.00
kmac_test_vectors_sha3_256 2017.530s 88841.072us 5 5 100.00
kmac_test_vectors_sha3_384 33.430s 1843.104us 5 5 100.00
kmac_test_vectors_sha3_512 1132.040s 62725.705us 5 5 100.00
kmac_test_vectors_shake_128 2624.200s 110559.701us 5 5 100.00
kmac_test_vectors_shake_256 2142.930s 173040.448us 5 5 100.00
kmac_test_vectors_kmac 3.120s 150.939us 5 5 100.00
kmac_test_vectors_kmac_xof 3.210s 135.034us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 444.820s 19712.982us 50 50 100.00
app 50 50 100.00
kmac_app 383.270s 159636.588us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 297.040s 14860.102us 10 10 100.00
entropy_refresh 49 50 98.00
kmac_entropy_refresh 469.790s 24563.321us 49 50 98.00
error 50 50 100.00
kmac_error 474.220s 82250.559us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 20.340s 13844.444us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.590s 977.386us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 36.500s 473.680us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 40.910s 5769.803us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 71.800s 13349.035us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 36.660s 1925.485us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3183.210s 149146.920us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.130s 24.867us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.240s 35.702us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.590s 677.834us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.590s 677.834us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.250s 141.582us 5 5 100.00
kmac_csr_rw 1.340s 42.580us 20 20 100.00
kmac_csr_aliasing 6.360s 533.807us 5 5 100.00
kmac_same_csr_outstanding 2.880s 352.568us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.250s 141.582us 5 5 100.00
kmac_csr_rw 1.340s 42.580us 20 20 100.00
kmac_csr_aliasing 6.360s 533.807us 5 5 100.00
kmac_same_csr_outstanding 2.880s 352.568us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.090s 55.828us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.090s 55.828us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.090s 55.828us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.090s 55.828us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 4.640s 298.714us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 5.690s 492.912us 20 20 100.00
kmac_sec_cm 104.010s 78752.303us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.690s 492.912us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 36.660s 1925.485us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 71.190s 5124.958us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 444.820s 19712.982us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.090s 55.828us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 104.010s 78752.303us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 104.010s 78752.303us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 104.010s 78752.303us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 71.190s 5124.958us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 36.660s 1925.485us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 104.010s 78752.303us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 344.850s 49612.391us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 71.190s 5124.958us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 253.180s 5012.284us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 611200286692847448041691150823491596986877594945733581315584496183692816446 263
UVM_ERROR @ 69497848 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3612818857 [0xd7573da9] vs 781581748 [0x2e95fdb4]) Regname: kmac_reg_block.prefix_6.prefix_0 reset value: 0x0
UVM_INFO @ 69497848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 86831143809272413463019706566006187749602218703255365527934998584968892058403 218
UVM_ERROR @ 5261707081 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 5261707081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_entropy_refresh 29332721598006796720840512869403708470744628117885510825837997230753009846859 79
UVM_ERROR @ 761451375 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 761451375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---