Simulation Results: kmac/unmasked

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.55 %
  • code
  • 92.21 %
  • assert
  • 97.90 %
  • func
  • 96.54 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 72.73 %
Validation stages
V1
100.00%
V2
98.18%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 72.510s 11825.789us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.270s 24.252us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.450s 34.273us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 13.490s 655.818us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.850s 496.168us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.790s 261.034us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.450s 34.273us 20 20 100.00
kmac_csr_aliasing 6.850s 496.168us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.100s 15.870us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.820s 38.131us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 2869.300s 264909.602us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 949.010s 116510.808us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2013.940s 384055.090us 5 5 100.00
kmac_test_vectors_sha3_256 1791.330s 352313.920us 5 5 100.00
kmac_test_vectors_sha3_384 1384.140s 72658.116us 5 5 100.00
kmac_test_vectors_sha3_512 751.700s 141161.351us 5 5 100.00
kmac_test_vectors_shake_128 2270.580s 104560.787us 5 5 100.00
kmac_test_vectors_shake_256 1812.410s 77401.170us 5 5 100.00
kmac_test_vectors_kmac 2.640s 104.305us 5 5 100.00
kmac_test_vectors_kmac_xof 3.440s 381.483us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 513.220s 190509.194us 50 50 100.00
app 50 50 100.00
kmac_app 370.910s 17356.933us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 350.590s 66445.985us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 319.780s 99923.273us 50 50 100.00
error 50 50 100.00
kmac_error 387.230s 112409.416us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 23.980s 23857.944us 50 50 100.00
sideload_invalid 36 50 72.00
kmac_sideload_invalid 96.960s 10012.086us 36 50 72.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 37.940s 1982.739us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 38.700s 11127.957us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 84.290s 8407.282us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 40.910s 1055.809us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3495.700s 336445.901us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.140s 14.846us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.230s 189.781us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.480s 1517.677us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.480s 1517.677us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.270s 24.252us 5 5 100.00
kmac_csr_rw 1.450s 34.273us 20 20 100.00
kmac_csr_aliasing 6.850s 496.168us 5 5 100.00
kmac_same_csr_outstanding 3.030s 363.854us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.270s 24.252us 5 5 100.00
kmac_csr_rw 1.450s 34.273us 20 20 100.00
kmac_csr_aliasing 6.850s 496.168us 5 5 100.00
kmac_same_csr_outstanding 3.030s 363.854us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.450s 78.736us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.450s 78.736us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.450s 78.736us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.450s 78.736us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 4.750s 177.207us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 5.120s 239.363us 20 20 100.00
kmac_sec_cm 69.050s 55948.436us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.120s 239.363us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 40.910s 1055.809us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 72.510s 11825.789us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 513.220s 190509.194us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.450s 78.736us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 69.050s 55948.436us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 69.050s 55948.436us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 69.050s 55948.436us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 72.510s 11825.789us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 40.910s 1055.809us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 69.050s 55948.436us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 329.030s 13470.251us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 72.510s 11825.789us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 256.760s 23847.105us 8 10 80.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 104927629369131768086565463472405966570494547557944245826427104757657742244785 80
UVM_FATAL @ 10142504235 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3c731000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10142504235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 72679309403382127664934226614806513452027951420007092865748076228966959426197 81
UVM_FATAL @ 10406471265 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc85c2000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10406471265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 46908882129153233924788517968803943488062015671735049956298262654299966154309 80
UVM_FATAL @ 10131733027 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x116c7000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10131733027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 71769673498958422438316888550318125071318533820193088253418338854693414256114 227
UVM_ERROR @ 14981799680 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14981799680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 25866477439638509245116821140165026418026954098860242079151187921813384317301 285
UVM_ERROR @ 6400085273 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6400085273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18)
kmac_sideload_invalid 46804140491465226113140447406305536541209616860226312063547912714037267420573 98
UVM_FATAL @ 10105636746 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4e266000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 10105636746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)
kmac_sideload_invalid 72648196163841090192256661171463479922025744928415165213940666144579469434100 88
UVM_FATAL @ 10931462511 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x301cf000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10931462511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 84866273448031419680253735854156446680643037863196962875916269771931110286441 78
UVM_FATAL @ 10033179688 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdb44b000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10033179688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 27212561556974000946084015466645220121246273738138944153081893306736485837457 83
UVM_FATAL @ 10031920086 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd0f28000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10031920086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 115769438477410148059644172080569272041510842447421020495211199954859218326045 83
UVM_FATAL @ 10012085977 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfb80000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10012085977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17)
kmac_sideload_invalid 40605108370160861727533189554176325056437190638021169255872555432026598871165 96
UVM_FATAL @ 10802746967 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xddb11000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10802746967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
kmac_sideload_invalid 98976515377344765104146086279049407439055925797877275683842327334971392929242 88
UVM_FATAL @ 10194695626 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x864db000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10194695626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)
kmac_sideload_invalid 51116271201859403843834926498989110929559972820744836457785262369096079571280 88
UVM_FATAL @ 10378291728 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcb829000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10378291728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27)
kmac_sideload_invalid 10291636904852528214502674866123911270282172863519083502017804256951834048472 106
UVM_FATAL @ 10581758510 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x815ae000, Comparison=CompareOpEq, exp_data=0x1, call_count=27)
UVM_INFO @ 10581758510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 79913364548939619523462719563128504344061867356271153263338584661765542171903 79
UVM_FATAL @ 10047658219 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb0728000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10047658219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22)
kmac_sideload_invalid 89108603129601831795557344255670943357078469671284845662140565258118138688409 108
UVM_FATAL @ 10574027830 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9cf05000, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10574027830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---