Simulation Results: lc_ctrl/volatile_unlock_disabled

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.52 %
  • code
  • 88.70 %
  • assert
  • 95.99 %
  • func
  • 95.86 %
  • line
  • 97.90 %
  • branch
  • 96.99 %
  • cond
  • 82.70 %
  • toggle
  • 91.35 %
  • FSM
  • 74.55 %
Validation stages
V1
100.00%
V2
99.73%
V2S
100.00%
V3
46.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 8.880s 369.155us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.290s 83.400us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.380s 72.231us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 1.950s 408.189us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.410s 66.997us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.860s 33.078us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.380s 72.231us 20 20 100.00
lc_ctrl_csr_aliasing 1.410s 66.997us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 9.300s 372.886us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 16.290s 1269.930us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.310s 27.220us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 3.940s 376.777us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 14.900s 1444.576us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 22.360s 887.543us 50 50 100.00
security_escalation 259 260 99.62
lc_ctrl_state_failure 14.900s 1444.576us 50 50 100.00
lc_ctrl_prog_failure 3.940s 376.777us 50 50 100.00
lc_ctrl_errors 22.360s 887.543us 50 50 100.00
lc_ctrl_security_escalation 12.940s 753.183us 50 50 100.00
lc_ctrl_jtag_state_failure 64.050s 8530.745us 20 20 100.00
lc_ctrl_jtag_prog_failure 30.500s 5715.335us 20 20 100.00
lc_ctrl_jtag_errors 83.430s 16470.346us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_csr_hw_reset 5.960s 1720.330us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.840s 141.146us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 35.170s 2244.738us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 13.940s 1171.138us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.850s 88.424us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.000s 226.773us 10 10 100.00
lc_ctrl_jtag_alert_test 2.850s 147.534us 10 10 100.00
lc_ctrl_jtag_smoke 17.750s 11325.158us 20 20 100.00
lc_ctrl_jtag_state_post_trans 26.350s 5797.609us 20 20 100.00
lc_ctrl_jtag_prog_failure 30.500s 5715.335us 20 20 100.00
lc_ctrl_jtag_errors 83.430s 16470.346us 19 20 95.00
lc_ctrl_jtag_access 33.350s 6793.705us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 27.650s 2627.535us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 36.930s 4373.499us 10 10 100.00
lc_ctrl_volatile_unlock 49 50 98.00
lc_ctrl_volatile_unlock_smoke 1.490s 16.512us 49 50 98.00
stress_all 50 50 100.00
lc_ctrl_stress_all 473.750s 116407.772us 50 50 100.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.720s 31.721us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.710s 222.595us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.710s 222.595us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.290s 83.400us 5 5 100.00
lc_ctrl_csr_rw 1.380s 72.231us 20 20 100.00
lc_ctrl_csr_aliasing 1.410s 66.997us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.860s 22.058us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.290s 83.400us 5 5 100.00
lc_ctrl_csr_rw 1.380s 72.231us 20 20 100.00
lc_ctrl_csr_aliasing 1.410s 66.997us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.860s 22.058us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 2.690s 346.549us 20 20 100.00
lc_ctrl_sec_cm 10.720s 1050.814us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 2.690s 346.549us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 16.290s 1269.930us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 14.900s 1444.576us 50 50 100.00
lc_ctrl_sec_cm 10.720s 1050.814us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 14.900s 1444.576us 50 50 100.00
lc_ctrl_sec_cm 10.720s 1050.814us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.900s 1444.576us 50 50 100.00
lc_ctrl_sec_cm 10.720s 1050.814us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.900s 1444.576us 50 50 100.00
lc_ctrl_sec_cm 10.720s 1050.814us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 14.900s 1444.576us 50 50 100.00
lc_ctrl_sec_cm 10.720s 1050.814us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.900s 1444.576us 50 50 100.00
lc_ctrl_sec_cm 10.720s 1050.814us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.900s 1444.576us 50 50 100.00
lc_ctrl_sec_cm 10.720s 1050.814us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 14.900s 1444.576us 50 50 100.00
lc_ctrl_sec_cm 10.720s 1050.814us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 12.940s 753.183us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 9.300s 372.886us 50 50 100.00
lc_ctrl_jtag_state_post_trans 26.350s 5797.609us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.210s 913.616us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.210s 913.616us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 17.000s 973.373us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.020s 3130.164us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.020s 3130.164us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 23 50 46.00
lc_ctrl_stress_all_with_rand_reset 102.400s 7689.034us 23 50 46.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 103834670410304199630777917001226208594214364007433734429243733424336888022373 3750
UVM_ERROR @ 3305488733 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3305488733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60897052074562708692090175866011450675501251937828750648134933135143758719244 5198
UVM_ERROR @ 1594375937 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1594375937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 38957732945238242006492629222768238759238898218789511122506536234612416385495 193
UVM_ERROR @ 111580170 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111580170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 103481170819534560560778725498749084904872037688675099900754722132075333215325 1548
UVM_ERROR @ 2318500282 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2318500282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 88745910849903726746951827043593925521122977198230189498050863093103797382148 2518
UVM_ERROR @ 2995719660 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2995719660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 38953448735605111904268561775828547342678977353065705926144385139385720793551 4009
UVM_ERROR @ 5227419176 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5227419176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16894549506748400667851668268397299620000407829912454736152929652653738730 449
UVM_ERROR @ 2336935914 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2336935914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 114899967210603334015789733530708756032905441522057273053004105433855091305673 151
UVM_ERROR @ 105745449 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 105745449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65279248231726434999087328177581163194788787972207848542389277420671585568427 154
UVM_ERROR @ 544638405 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 544638405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 5905221979107507698128274975430311821740297008031908418898892313087065425277 1039
UVM_ERROR @ 859016598 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 859016598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14377306475545765171886563676451348825642285229185743221680142225137744062630 8266
UVM_ERROR @ 4429780922 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4429780922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 48857764537551662836604742872112014387755743530077051632081171046077405881074 151
UVM_ERROR @ 106356818 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 106356818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 56203621935079437068338034872424998833318898523430333478428200389911059692692 2875
UVM_ERROR @ 5026710116 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5026710116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34662835346359636222661001556375577677163138863671969530778494567806245591634 450
UVM_ERROR @ 710345489 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 710345489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108288486449074245879870132193127636185300688231888361883555148523512952368812 1679
UVM_ERROR @ 9547208579 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9547208579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 40557995070017413481543891916205671310158656240698901424764695599050034400085 154
UVM_ERROR @ 526186674 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 526186674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 87051510779423188281183649478983006111551215155927239401636243671525993412183 5827
UVM_ERROR @ 6646394175 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6646394175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14666269492347411974094014493447184557277300989056898464379313016111467057096 298
UVM_ERROR @ 315982622 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 315982622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 80378245962875277900344744176638453117915922697676265806183677410647449092150 6291
UVM_ERROR @ 4208320138 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4208320138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105353144631968636999860337619156028378517621064419314529533894860600840120870 5365
UVM_ERROR @ 7689033502 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7689033502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96212964914586876503768717642277446455753538071288428868060598842852902703344 1614
UVM_ERROR @ 4239954120 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4239954120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 94655311015223835238917745092901699172982612582989721385117140958803517915478 151
UVM_ERROR @ 428252396 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 428252396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29120373186268992501430622276210290529897876670118302263372826002064940015829 17190
UVM_ERROR @ 22937633620 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 22937633620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 70751785231243424852462788544011487624941174787833330842687137316942592603815 10745
UVM_ERROR @ 13870453121 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 13870453121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 38475857180494941646630417293703078220230056337823483174758905182924886382552 12881
UVM_ERROR @ 2860754607 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 2860754607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 112302319488299464865893926395365309253500547032349494924010549806000490443434 2999
UVM_ERROR @ 2592710206 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 2592710206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_jtag_errors 40749339648951208090472839550457705684352636386365879536052401743284226330660 1206
UVM_ERROR @ 518455484 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 518455484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69153792466294329218331169447597125338949687733118251988705388840830286914715 771
UVM_ERROR @ 113610339 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 113610339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout lc_ctrl_regs_reg_block.status.token_error (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1)
lc_ctrl_volatile_unlock_smoke 49944811635076354301163268175383196514370826178954250061135590116732187185370 148
UVM_FATAL @ 113581128 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout lc_ctrl_regs_reg_block.status.token_error (addr=0xc68f04, Comparison=CompareOpEq, exp_data=0x1, call_count=1)
UVM_INFO @ 113581128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---