Simulation Results

Simulation Results: otbn

24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
97.76 %

code
96.55 %

assert
96.73 %

func
100.00 %

block
99.47 %

line
99.65 %

branch
93.17 %

toggle
93.39 %

FSM
100.00 %

Validation stages

V1		99.40%
V2		96.74%
V2S		95.28%
V3		30.00%
unmapped		100.00%

165/166 passed

99.40 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				0	1	0.00
	otbn_smoke	21.332s	0.000us	0	1	0.00
single_binary				100	100	100.00
	otbn_single	56.000s	246.637us	100	100	100.00
csr_hw_reset				5	5	100.00
	otbn_csr_hw_reset	5.000s	45.086us	5	5	100.00
csr_rw				20	20	100.00
	otbn_csr_rw	5.000s	37.072us	20	20	100.00
csr_bit_bash				5	5	100.00
	otbn_csr_bit_bash	9.000s	149.925us	5	5	100.00
csr_aliasing				5	5	100.00
	otbn_csr_aliasing	5.000s	14.462us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	otbn_csr_mem_rw_with_rand_reset	14.000s	47.356us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	otbn_csr_rw	5.000s	37.072us	20	20	100.00
	otbn_csr_aliasing	5.000s	14.462us	5	5	100.00
mem_walk				5	5	100.00
	otbn_mem_walk	95.000s	1989.131us	5	5	100.00
mem_partial_access				5	5	100.00
	otbn_mem_partial_access	56.000s	2091.811us	5	5	100.00

267/276 passed

96.74 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reset_recovery				10	10	100.00
	otbn_reset	56.000s	343.989us	10	10	100.00
multi_error				1	1	100.00
	otbn_multi_err	46.000s	562.190us	1	1	100.00
back_to_back				10	10	100.00
	otbn_multi	163.000s	506.425us	10	10	100.00
stress_all				9	10	90.00
	otbn_stress_all	98.000s	807.674us	9	10	90.00
lc_escalation				57	60	95.00
	otbn_escalate	21.000s	160.591us	57	60	95.00
zero_state_err_urnd				0	5	0.00
	otbn_zero_state_err_urnd	6.000s	35.550us	0	5	0.00
sw_errs_fatal_chk				10	10	100.00
	otbn_sw_errs_fatal_chk	22.000s	150.208us	10	10	100.00
alert_test				50	50	100.00
	otbn_alert_test	6.000s	25.926us	50	50	100.00
intr_test				50	50	100.00
	otbn_intr_test	5.000s	15.892us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	otbn_tl_errors	9.000s	82.611us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	otbn_tl_errors	9.000s	82.611us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	otbn_csr_hw_reset	5.000s	45.086us	5	5	100.00
	otbn_csr_rw	5.000s	37.072us	20	20	100.00
	otbn_csr_aliasing	5.000s	14.462us	5	5	100.00
	otbn_same_csr_outstanding	6.000s	17.982us	20	20	100.00
tl_d_partial_access				50	50	100.00
	otbn_csr_hw_reset	5.000s	45.086us	5	5	100.00
	otbn_csr_rw	5.000s	37.072us	20	20	100.00
	otbn_csr_aliasing	5.000s	14.462us	5	5	100.00
	otbn_same_csr_outstanding	6.000s	17.982us	20	20	100.00

V2S

323/339 passed

95.28 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
mem_integrity				25	25	100.00
	otbn_imem_err	11.000s	23.740us	10	10	100.00
	otbn_dmem_err	11.000s	26.407us	15	15	100.00
internal_integrity				15	17	88.24
	otbn_alu_bignum_mod_err	10.000s	403.400us	5	5	100.00
	otbn_controller_ispr_rdata_err	9.000s	20.348us	5	5	100.00
	otbn_mac_bignum_acc_err	11.000s	118.915us	5	5	100.00
	otbn_urnd_err	5.000s	8.069us	0	2	0.00
illegal_bus_access				5	5	100.00
	otbn_illegal_mem_acc	9.000s	29.969us	5	5	100.00
otbn_mem_gnt_acc_err				2	2	100.00
	otbn_mem_gnt_acc_err	9.000s	24.971us	2	2	100.00
otbn_non_sec_partial_wipe				9	10	90.00
	otbn_partial_wipe	11.000s	60.302us	9	10	90.00
tl_intg_err				25	25	100.00
	otbn_tl_intg_err	37.000s	197.108us	20	20	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
passthru_mem_tl_intg_err				17	20	85.00
	otbn_passthru_mem_tl_intg_err	70.000s	404.997us	17	20	85.00
prim_fsm_check				5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
prim_count_check				5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
sec_cm_mem_scramble				0	1	0.00
	otbn_smoke	21.332s	0.000us	0	1	0.00
sec_cm_data_mem_integrity				15	15	100.00
	otbn_dmem_err	11.000s	26.407us	15	15	100.00
sec_cm_instruction_mem_integrity				10	10	100.00
	otbn_imem_err	11.000s	23.740us	10	10	100.00
sec_cm_bus_integrity				20	20	100.00
	otbn_tl_intg_err	37.000s	197.108us	20	20	100.00
sec_cm_controller_fsm_global_esc				57	60	95.00
	otbn_escalate	21.000s	160.591us	57	60	95.00
sec_cm_controller_fsm_local_esc				35	40	87.50
	otbn_imem_err	11.000s	23.740us	10	10	100.00
	otbn_dmem_err	11.000s	26.407us	15	15	100.00
	otbn_zero_state_err_urnd	6.000s	35.550us	0	5	0.00
	otbn_illegal_mem_acc	9.000s	29.969us	5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
sec_cm_controller_fsm_sparse				5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
sec_cm_scramble_key_sideload				100	100	100.00
	otbn_single	56.000s	246.637us	100	100	100.00
sec_cm_scramble_ctrl_fsm_local_esc				35	40	87.50
	otbn_imem_err	11.000s	23.740us	10	10	100.00
	otbn_dmem_err	11.000s	26.407us	15	15	100.00
	otbn_zero_state_err_urnd	6.000s	35.550us	0	5	0.00
	otbn_illegal_mem_acc	9.000s	29.969us	5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
sec_cm_scramble_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_global_esc				57	60	95.00
	otbn_escalate	21.000s	160.591us	57	60	95.00
sec_cm_start_stop_ctrl_fsm_local_esc				35	40	87.50
	otbn_imem_err	11.000s	23.740us	10	10	100.00
	otbn_dmem_err	11.000s	26.407us	15	15	100.00
	otbn_zero_state_err_urnd	6.000s	35.550us	0	5	0.00
	otbn_illegal_mem_acc	9.000s	29.969us	5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
sec_cm_data_reg_sw_sca				100	100	100.00
	otbn_single	56.000s	246.637us	100	100	100.00
sec_cm_ctrl_redun				12	12	100.00
	otbn_ctrl_redun	8.000s	73.578us	12	12	100.00
sec_cm_pc_ctrl_flow_redun				5	5	100.00
	otbn_pc_ctrl_flow_redun	12.000s	49.859us	5	5	100.00
sec_cm_rnd_bus_consistency				5	5	100.00
	otbn_rnd_sec_cm	55.000s	258.380us	5	5	100.00
sec_cm_rnd_rng_digest				5	5	100.00
	otbn_rnd_sec_cm	55.000s	258.380us	5	5	100.00
sec_cm_rf_base_data_reg_sw_integrity				10	10	100.00
	otbn_rf_base_intg_err	11.000s	28.595us	10	10	100.00
sec_cm_rf_base_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
sec_cm_stack_wr_ptr_ctr_redun				5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
sec_cm_rf_bignum_data_reg_sw_integrity				10	10	100.00
	otbn_rf_bignum_intg_err	14.000s	86.923us	10	10	100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
sec_cm_loop_stack_ctr_redun				5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00
sec_cm_loop_stack_addr_integrity				4	5	80.00
	otbn_stack_addr_integ_chk	19.000s	35.784us	4	5	80.00
sec_cm_call_stack_addr_integrity				4	5	80.00
	otbn_stack_addr_integ_chk	19.000s	35.784us	4	5	80.00
sec_cm_start_stop_ctrl_state_consistency				7	7	100.00
	otbn_sec_wipe_err	11.000s	42.876us	7	7	100.00
sec_cm_data_mem_sec_wipe				100	100	100.00
	otbn_single	56.000s	246.637us	100	100	100.00
sec_cm_instruction_mem_sec_wipe				100	100	100.00
	otbn_single	56.000s	246.637us	100	100	100.00
sec_cm_data_reg_sw_sec_wipe				100	100	100.00
	otbn_single	56.000s	246.637us	100	100	100.00
sec_cm_write_mem_integrity				10	10	100.00
	otbn_multi	163.000s	506.425us	10	10	100.00
sec_cm_ctrl_flow_count				100	100	100.00
	otbn_single	56.000s	246.637us	100	100	100.00
sec_cm_ctrl_flow_sca				100	100	100.00
	otbn_single	56.000s	246.637us	100	100	100.00
sec_cm_data_mem_sw_noaccess				5	5	100.00
	otbn_sw_no_acc	23.000s	123.348us	5	5	100.00
sec_cm_key_sideload				100	100	100.00
	otbn_single	56.000s	246.637us	100	100	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	otbn_sec_cm	241.000s	5815.069us	5	5	100.00

3/10 passed

30.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				3	10	30.00
	otbn_stress_all_with_rand_reset	795.000s	19052.232us	3	10	30.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	otbn_smoke_vectorized	8.000s	217.158us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
	otbn_passthru_mem_tl_intg_err	46811874034364971647265330933088912011482547023333900592853265520478205235797	86	UVM_FATAL @ 25628618 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived. UVM_INFO @ 25628618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_passthru_mem_tl_intg_err	220339985353914832915499856035654727720274933190806699864194924487240084164	86	UVM_FATAL @ 2510544 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived. UVM_INFO @ 2510544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_escalate	20520101554372696724910732582308269598384576169207051137252101547787201337142	117	UVM_FATAL @ 31288263 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived. UVM_INFO @ 31288263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
	otbn_passthru_mem_tl_intg_err	88448711504521394967089967592032416489580364298043483648033932208236512363087	86	UVM_FATAL @ 2455192 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived. UVM_INFO @ 2455192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job returned non-zero exit code
	otbn_smoke	100181045188693697887326429254069191373739704678742973266944285985333342342985	None	[make]: pre_run mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --src-dir /nightly/current_run/opentitan/hw/ip/otbn/dv/smoke /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest/otbn-binaries /nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest 2026/04/25 02:35:19 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64... Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
	otbn_stress_all	103238407781906530228503566369485914154925404486508673668664120767986290331489	None	[make]: pre_run mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 103238407781906530228503566369485914154925404486508673668664120767986290331489 --size 2000 --count 10 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest/otbn-binaries /nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest 2026/04/25 02:35:20 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64... Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	otbn_stress_all_with_rand_reset	35212845825207707729102285136307501292406220278159226949535894069844253417591	188	UVM_ERROR @ 1590152470 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1590152470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	31414901528242956106762778102893087886725522837526508410067304155593059657475	314	UVM_ERROR @ 722277050 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 722277050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	18224934042298943509922316559870719143994435881672739309001491797519050678902	304	UVM_ERROR @ 1172479099 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1172479099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	44481213195716564682484155408901293641570329036626509003485675211897935225965	418	UVM_ERROR @ 2997861331 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 2997861331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
	otbn_zero_state_err_urnd	14514666919103090247731748352952298954155737071433788569582928518737865987543	117	UVM_ERROR @ 8227130 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) UVM_INFO @ 8227130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_zero_state_err_urnd	69653088063025090899800802741761195467688661383497261417851593219433617225329	120	UVM_ERROR @ 35549854 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) UVM_INFO @ 35549854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_zero_state_err_urnd	104220252455165237079905341619859546173224913788439805773639577632079712007001	112	UVM_ERROR @ 34044039 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) UVM_INFO @ 34044039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_zero_state_err_urnd	60539671391004024494037635508669703782838167098388462540316459174662320761060	105	UVM_ERROR @ 19746451 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) UVM_INFO @ 19746451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_zero_state_err_urnd	18788001217058787463854494180387810401173884548517277232915630302844697751532	106	UVM_ERROR @ 5136282 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) UVM_INFO @ 5136282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
	otbn_urnd_err	111674778992267839629152039936909337924888532571937601571145580036173004982916	119	UVM_ERROR @ 3162860 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) UVM_INFO @ 3162860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_urnd_err	6940741233438548456633253397584356071522274143402912252671339809347951760633	111	UVM_ERROR @ 8069259 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) UVM_INFO @ 8069259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
	otbn_stack_addr_integ_chk	102862273654590323957505052554798620949470683322702966993181249621902348218506	121	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 5787615 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed UVM_ERROR @ 5787615 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 5787615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_escalate	100909794008629726402749209077082528456322756000711406116430750576305545365591	116	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 57622280 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed UVM_ERROR @ 57622280 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 57622280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
	otbn_stress_all_with_rand_reset	61928975615231169366085877567632118692633146223796281974147130128596090825500	243	UVM_FATAL @ 1127961712 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset) UVM_INFO @ 1127961712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
	otbn_stress_all_with_rand_reset	43729889908033507403133131658937209454130364148646832350224217983733838013704	237	UVM_FATAL @ 143443938 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset) UVM_INFO @ 143443938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	58970950979863195370279301384544627194552137792471559054596665747324907645424	232	UVM_FATAL @ 5481222979 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset) UVM_INFO @ 5481222979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_/tb.sv,292): Assertion MatchingStatus_A has failed
	otbn_partial_wipe	63872583018176857180266311274167309068209942840386332018761589453300391702561	108	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 6717455 PS) Assertion tb.MatchingStatus_A has failed UVM_ERROR @ 6717455 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A UVM_INFO @ 6717455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [] vs [*]) value for register otbn_reg_block.status
	otbn_escalate	19170887259785311093353408724429097816879299518509275078388272287784393791435	113	UVM_ERROR @ 1544037 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status UVM_INFO @ 1544037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---