Simulation Results

Simulation Results: rom_ctrl/32kb

24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.59 %

code
99.68 %

assert
96.80 %

func
99.28 %

line
99.59 %

branch
100.00 %

cond
98.81 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		94.20%
V3		100.00%

67/67 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	5.350s	2131.910us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	9.780s	301.661us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	7.840s	2076.549us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	6.770s	297.035us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	7.300s	174.190us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	8.090s	325.488us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	7.840s	2076.549us	20	20	100.00
	rom_ctrl_csr_aliasing	7.300s	174.190us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	6.800s	171.424us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	6.350s	166.415us	5	5	100.00

144/144 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	7.010s	227.894us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	23.610s	588.561us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	9.870s	1087.923us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	8.710s	4130.850us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	12.390s	215.676us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	12.390s	215.676us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	9.780s	301.661us	5	5	100.00
	rom_ctrl_csr_rw	7.840s	2076.549us	20	20	100.00
	rom_ctrl_csr_aliasing	7.300s	174.190us	5	5	100.00
	rom_ctrl_same_csr_outstanding	10.030s	570.128us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	9.780s	301.661us	5	5	100.00
	rom_ctrl_csr_rw	7.840s	2076.549us	20	20	100.00
	rom_ctrl_csr_aliasing	7.300s	174.190us	5	5	100.00
	rom_ctrl_same_csr_outstanding	10.030s	570.128us	20	20	100.00

V2S

65/69 passed

94.20 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	98.910s	11589.054us	16	20	80.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	33.000s	876.403us	20	20	100.00
tl_intg_err				25	25	100.00
	rom_ctrl_tl_intg_err	60.510s	1326.444us	20	20	100.00
	rom_ctrl_sec_cm	225.220s	1348.653us	5	5	100.00
prim_fsm_check				5	5	100.00
	rom_ctrl_sec_cm	225.220s	1348.653us	5	5	100.00
prim_count_check				5	5	100.00
	rom_ctrl_sec_cm	225.220s	1348.653us	5	5	100.00
sec_cm_checker_ctr_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	98.910s	11589.054us	16	20	80.00
sec_cm_checker_ctrl_flow_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	98.910s	11589.054us	16	20	80.00
sec_cm_checker_fsm_local_esc				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	98.910s	11589.054us	16	20	80.00
sec_cm_compare_ctrl_flow_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	98.910s	11589.054us	16	20	80.00
sec_cm_compare_ctr_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	98.910s	11589.054us	16	20	80.00
sec_cm_compare_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	225.220s	1348.653us	5	5	100.00
sec_cm_fsm_sparse				5	5	100.00
	rom_ctrl_sec_cm	225.220s	1348.653us	5	5	100.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	5.350s	2131.910us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	5.350s	2131.910us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	5.350s	2131.910us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	60.510s	1326.444us	20	20	100.00
sec_cm_bus_local_esc				18	22	81.82
	rom_ctrl_corrupt_sig_fatal_chk	98.910s	11589.054us	16	20	80.00
	rom_ctrl_kmac_err_chk	9.870s	1087.923us	2	2	100.00
sec_cm_mux_mubi				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	98.910s	11589.054us	16	20	80.00
sec_cm_mux_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	98.910s	11589.054us	16	20	80.00
sec_cm_ctrl_redun				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	98.910s	11589.054us	16	20	80.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	33.000s	876.403us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	225.220s	1348.653us	5	5	100.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	491.980s	16875.720us	20	20	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
	rom_ctrl_corrupt_sig_fatal_chk	56650428566749227787814801147416068266443370625866654274511666325264148403334	94	UVM_ERROR @ 3779648740 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 3779648740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	8159709801831304967079252885682285927161024903317993133815503831799564724887	98	UVM_ERROR @ 4712016839 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 4712016839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	9124099904627713832410639530635892037035937696752668432788120232922311475494	94	UVM_ERROR @ 564863470 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 564863470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	6227081387877082049552212082503806170865371502774046840409375492479101360581	94	UVM_ERROR @ 960807982 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 960807982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---