| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 10.410s | 767.749us | 2 | 2 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 15.350s | 232.129us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rom_ctrl_csr_rw | 11.660s | 296.245us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_bit_bash | 10.320s | 214.996us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_aliasing | 13.650s | 1030.083us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 12.870s | 1068.939us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rom_ctrl_csr_rw | 11.660s | 296.245us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 13.650s | 1030.083us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| rom_ctrl_mem_walk | 9.400s | 1067.179us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| rom_ctrl_mem_partial_access | 12.550s | 297.885us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_max_throughput_chk | 14.110s | 1324.113us | 2 | 2 | 100.00 | |
| stress_all | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all | 66.480s | 4173.055us | 20 | 20 | 100.00 | |
| kmac_err_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_kmac_err_chk | 19.630s | 397.235us | 2 | 2 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rom_ctrl_alert_test | 16.140s | 4143.748us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_errors | 15.930s | 1071.667us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_errors | 15.930s | 1071.667us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 15.350s | 232.129us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_rw | 11.660s | 296.245us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 13.650s | 1030.083us | 5 | 5 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 14.970s | 1450.833us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 15.350s | 232.129us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_rw | 11.660s | 296.245us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 13.650s | 1030.083us | 5 | 5 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 14.970s | 1450.833us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 276.340s | 92865.696us | 20 | 20 | 100.00 | |
| passthru_mem_tl_intg_err | 20 | 20 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 53.130s | 6921.525us | 20 | 20 | 100.00 | |
| tl_intg_err | 25 | 25 | 100.00 | |||
| rom_ctrl_sec_cm | 584.990s | 2502.436us | 5 | 5 | 100.00 | |
| rom_ctrl_tl_intg_err | 134.740s | 619.532us | 20 | 20 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 584.990s | 2502.436us | 5 | 5 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 584.990s | 2502.436us | 5 | 5 | 100.00 | |
| sec_cm_checker_ctr_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 276.340s | 92865.696us | 20 | 20 | 100.00 | |
| sec_cm_checker_ctrl_flow_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 276.340s | 92865.696us | 20 | 20 | 100.00 | |
| sec_cm_checker_fsm_local_esc | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 276.340s | 92865.696us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctrl_flow_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 276.340s | 92865.696us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctr_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 276.340s | 92865.696us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctr_redun | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 584.990s | 2502.436us | 5 | 5 | 100.00 | |
| sec_cm_fsm_sparse | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 584.990s | 2502.436us | 5 | 5 | 100.00 | |
| sec_cm_mem_scramble | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 10.410s | 767.749us | 2 | 2 | 100.00 | |
| sec_cm_mem_digest | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 10.410s | 767.749us | 2 | 2 | 100.00 | |
| sec_cm_intersig_mubi | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 10.410s | 767.749us | 2 | 2 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_intg_err | 134.740s | 619.532us | 20 | 20 | 100.00 | |
| sec_cm_bus_local_esc | 22 | 22 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 276.340s | 92865.696us | 20 | 20 | 100.00 | |
| rom_ctrl_kmac_err_chk | 19.630s | 397.235us | 2 | 2 | 100.00 | |
| sec_cm_mux_mubi | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 276.340s | 92865.696us | 20 | 20 | 100.00 | |
| sec_cm_mux_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 276.340s | 92865.696us | 20 | 20 | 100.00 | |
| sec_cm_ctrl_redun | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 276.340s | 92865.696us | 20 | 20 | 100.00 | |
| sec_cm_ctrl_mem_integrity | 20 | 20 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 53.130s | 6921.525us | 20 | 20 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 584.990s | 2502.436us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 407.750s | 5388.111us | 20 | 20 | 100.00 | |