Simulation Results: rstmgr

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.56 %
  • code
  • 99.59 %
  • assert
  • 97.62 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.97%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.850s 69.801us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.090s 65.877us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 0.960s 37.258us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 3.980s 195.988us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.360s 52.957us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.560s 96.939us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 0.960s 37.258us 20 20 100.00
rstmgr_csr_aliasing 1.360s 52.957us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.930s 149.975us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 1.330s 48.637us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.480s 88.558us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 6.500s 828.662us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 6.500s 828.662us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 6.500s 828.662us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 6.500s 828.662us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 45.870s 6217.224us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.570s 50.497us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 2.470s 89.388us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 2.470s 89.388us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.090s 65.877us 5 5 100.00
rstmgr_csr_rw 0.960s 37.258us 20 20 100.00
rstmgr_csr_aliasing 1.360s 52.957us 5 5 100.00
rstmgr_same_csr_outstanding 1.290s 65.444us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.090s 65.877us 5 5 100.00
rstmgr_csr_rw 0.960s 37.258us 20 20 100.00
rstmgr_csr_aliasing 1.360s 52.957us 5 5 100.00
rstmgr_same_csr_outstanding 1.290s 65.444us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_tl_intg_err 4.100s 644.353us 20 20 100.00
rstmgr_sec_cm 41.170s 8325.961us 5 5 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 41.170s 8325.961us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 41.170s 8325.961us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 4.100s 644.353us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.660s 59.425us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 48 50 96.00
rstmgr_leaf_rst_cnsty 4.490s 464.667us 48 50 96.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 3.520s 291.571us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 41.170s 8325.961us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 0.960s 37.258us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 0.960s 37.258us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:*
rstmgr_leaf_rst_cnsty 8053458128516287410220423260541623619627454114060483295396189172643891444792 135
UVM_ERROR @ 283749192 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
UVM_INFO @ 283749192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rstmgr_leaf_rst_cnsty 99423000133567012185625419829589229448306842409314559835937321750356242209969 121
UVM_ERROR @ 237174184 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
UVM_INFO @ 237174184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---