| V1 |
|
100.00% |
| V2 |
|
92.08% |
| V2S |
|
100.00% |
| V3 |
|
57.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.980s | 841.782us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.940s | 17.572us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.980s | 17.073us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 3.530s | 304.143us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 1.140s | 52.776us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.590s | 106.869us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.980s | 17.073us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.140s | 52.776us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 1 | 20 | 5.00 | |||
| rv_timer_random_reset | 3.550s | 2115.813us | 1 | 20 | 5.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 4.670s | 1922.641us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 1049.850s | 1144394.991us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 1049.850s | 1144394.991us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 8.070s | 6531.178us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.890s | 17.590us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.930s | 11.365us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 3.080s | 653.118us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 3.080s | 653.118us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.940s | 17.572us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.980s | 17.073us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.140s | 52.776us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.190s | 152.789us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.940s | 17.572us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.980s | 17.073us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.140s | 52.776us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.190s | 152.789us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 1.320s | 366.412us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.910s | 134.630us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.910s | 134.630us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 3 | 10 | 30.00 | |||
| rv_timer_min | 1.000s | 129.452us | 3 | 10 | 30.00 | |
| max_value | 3 | 10 | 30.00 | |||
| rv_timer_max | 2.190s | 86.251us | 3 | 10 | 30.00 | |
| stress_all_with_rand_reset | 17 | 20 | 85.00 | |||
| rv_timer_stress_all_with_rand_reset | 71.420s | 7107.086us | 17 | 20 | 85.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_min | 109141635690293069757673698562485703201206399589329662093380837330215205474894 | 77 |
UVM_FATAL @ 317122980 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2c539904) == 0x1
UVM_INFO @ 317122980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 40991407297555736755686092319687901047427769063227419635963150071002271875876 | 76 |
UVM_FATAL @ 150976269 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x86383d04) == 0x1
UVM_INFO @ 150976269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 105537907143793232885205586963403002569708548112700558846839357495140715216448 | 76 |
UVM_FATAL @ 290008148 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3821f104) == 0x1
UVM_INFO @ 290008148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 45938858315423707060598404261723820269979366628903072256366564522761463716305 | 75 |
UVM_FATAL @ 460771194 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc2dfc704) == 0x1
UVM_INFO @ 460771194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 19533075964603809026077710981401774904309656580900246115302025120891444291381 | 75 |
UVM_FATAL @ 114831395 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x53f12f04) == 0x1
UVM_INFO @ 114831395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 28396068630860902205824456131613234203462697864623449605132596889011228680164 | 75 |
UVM_FATAL @ 360398124 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xff72a304) == 0x1
UVM_INFO @ 360398124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 107604671858761808687944759607305761892606735734993864571566196973861074875261 | 75 |
UVM_FATAL @ 297268265 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x25cafb04) == 0x1
UVM_INFO @ 297268265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 41245925823968280797908598760452871955997190139769552264085315988737780848950 | 76 |
UVM_FATAL @ 382082708 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc67c4d04) == 0x1
UVM_INFO @ 382082708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 71080725619397149790965551718204880283919022329337987980136062757217211505089 | 76 |
UVM_FATAL @ 121117639 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe2c39904) == 0x1
UVM_INFO @ 121117639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 99812357711440731040058670392553530487623832717229492697940994693188273696057 | 75 |
UVM_FATAL @ 2115812546 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x55c66d04) == 0x1
UVM_INFO @ 2115812546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 68941677677717843947177860916539020110810689434103212047301933165183119282020 | 76 |
UVM_FATAL @ 294231848 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf5ccd104) == 0x1
UVM_INFO @ 294231848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 11305071006113730951674627053016102560530347896108422082902467957789486634551 | 75 |
UVM_FATAL @ 502952869 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4a6e304) == 0x1
UVM_INFO @ 502952869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 38388747390602462856133404870141770447330107573808300595223884711114726439933 | 75 |
UVM_FATAL @ 1310922017 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2c644104) == 0x1
UVM_INFO @ 1310922017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 67405222595266745432603521133730502333101918614175207900193348319477996870160 | 75 |
UVM_FATAL @ 129452159 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd5793704) == 0x1
UVM_INFO @ 129452159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 103544058737608435416822624176801408344543070191073196181599088020614226142996 | 75 |
UVM_FATAL @ 97536209 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x43181304) == 0x1
UVM_INFO @ 97536209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 19519095535102788876969090126904202091199016462092550535585328415231225803630 | 77 |
UVM_FATAL @ 82121360 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x35dd2f04) == 0x1
UVM_INFO @ 82121360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 78151459203624326996418654242223241494605740967748838347180353621208323567447 | 76 |
UVM_FATAL @ 154411856 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3bb32304) == 0x1
UVM_INFO @ 154411856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 26232329936780225669478945625578516027005021376524549387384491821545097855932 | 75 |
UVM_FATAL @ 84774020 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xbba7904) == 0x1
UVM_INFO @ 84774020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 46190244858377225789004366317249998987168655631407935320915226572521409589710 | 75 |
UVM_FATAL @ 78677437 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc622704) == 0x1
UVM_INFO @ 78677437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 7491105498629338302627298933175348059228663623409119338932441458694250990661 | 77 |
UVM_FATAL @ 1830405644 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa77b2f04) == 0x1
UVM_INFO @ 1830405644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 103374966181200976221136207335207669900100977002256901893541320208418301485432 | 75 |
UVM_FATAL @ 197505381 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe60c6104) == 0x1
UVM_INFO @ 197505381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 114227963442377847767503565015832075806874089062992046297755649893347812931020 | 75 |
UVM_FATAL @ 1602278188 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd4cd7d04) == 0x1
UVM_INFO @ 1602278188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 94921044358000258026818870858086005105682912051555063968935031606935188075861 | 75 |
UVM_FATAL @ 310489728 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xcc9c6f04) == 0x1
UVM_INFO @ 310489728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 4651798455808177154465727398687321755004234531750565716124158963770975913110 | 75 |
UVM_FATAL @ 499899207 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8b725f04) == 0x1
UVM_INFO @ 499899207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 70717301665196759673396348079691632454698076822673207853035874856063027213240 | 75 |
UVM_FATAL @ 118181040 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc7a26b04) == 0x1
UVM_INFO @ 118181040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 73933069796062669877518768094275576025883795391873818227104700472845851025263 | 75 |
UVM_FATAL @ 407527620 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x62a27904) == 0x1
UVM_INFO @ 407527620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 33414908491275851415096841734744536432516586124334045334772685673664681323499 | 75 |
UVM_ERROR @ 45070531 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 45070531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 40013211637904152981861974462571740901850039363435057155769355240935671628962 | 75 |
UVM_ERROR @ 467434044 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 467434044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 85678349213323469152893056127330661380172798424752948406038543696018870302719 | 75 |
UVM_ERROR @ 707514614 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 707514614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 100233545609920309965899523113248594181107202085281396460880795046645719431370 | 75 |
UVM_ERROR @ 172282994 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 172282994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 98306196030341650362562980071946692657384427855408222282251017840794640753555 | 75 |
UVM_ERROR @ 43474328 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 43474328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 55830169889104767068384141850537532001758478336726735445597419326755345682490 | 75 |
UVM_ERROR @ 354189902 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 354189902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 84130255643716830970004422255277411206838245927856949341287179315834519095769 | 75 |
UVM_ERROR @ 86250937 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 86250937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 110785250743724265218764562237933703249315555645491172691715786789809843712187 | 123 |
UVM_ERROR @ 5889897080 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 5889897080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 94877823385132856356110052407390738708948687358130128948361027438235214533919 | 195 |
UVM_FATAL @ 2326004492 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 2326004492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 113018373159805105962603569593587134965687957137347000144483567926546419808436 | 234 |
UVM_FATAL @ 21248049577 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 21248049577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|