Simulation Results

Simulation Results: spi_host

24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.83 %

code
95.08 %

assert
95.64 %

func
90.76 %

block
97.05 %

line
98.76 %

branch
93.55 %

toggle
88.02 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.35%
V2S		100.00%
unmapped		100.00%

115/115 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_host_smoke	71.000s	8056.552us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_host_csr_hw_reset	2.000s	20.673us	5	5	100.00
csr_rw				20	20	100.00
	spi_host_csr_rw	2.000s	19.637us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_host_csr_bit_bash	3.000s	161.398us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_host_csr_aliasing	2.000s	68.027us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_host_csr_mem_rw_with_rand_reset	2.000s	68.809us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_host_csr_rw	2.000s	19.637us	20	20	100.00
	spi_host_csr_aliasing	2.000s	68.027us	5	5	100.00
mem_walk				5	5	100.00
	spi_host_mem_walk	2.000s	23.095us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_host_mem_partial_access	2.000s	29.816us	5	5	100.00

765/770 passed

99.35 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
performance				50	50	100.00
	spi_host_performance	3.000s	303.524us	50	50	100.00
error_event_intr				150	150	100.00
	spi_host_overflow_underflow	41.000s	2050.517us	50	50	100.00
	spi_host_error_cmd	2.000s	83.014us	50	50	100.00
	spi_host_event	230.000s	159053.963us	50	50	100.00
clock_rate				50	50	100.00
	spi_host_speed	6.000s	596.925us	50	50	100.00
speed				50	50	100.00
	spi_host_speed	6.000s	596.925us	50	50	100.00
chip_select_timing				50	50	100.00
	spi_host_speed	6.000s	596.925us	50	50	100.00
sw_reset				50	50	100.00
	spi_host_sw_reset	125.000s	5358.789us	50	50	100.00
passthrough_mode				50	50	100.00
	spi_host_passthrough_mode	2.000s	23.782us	50	50	100.00
cpol_cpha				50	50	100.00
	spi_host_speed	6.000s	596.925us	50	50	100.00
full_cycle				50	50	100.00
	spi_host_speed	6.000s	596.925us	50	50	100.00
duplex				50	50	100.00
	spi_host_smoke	71.000s	8056.552us	50	50	100.00
tx_rx_only				50	50	100.00
	spi_host_smoke	71.000s	8056.552us	50	50	100.00
stress_all				47	50	94.00
	spi_host_stress_all	2195.000s	1000000.000us	47	50	94.00
spien				49	50	98.00
	spi_host_spien	354.000s	17324.650us	49	50	98.00
stall				49	50	98.00
	spi_host_status_stall	504.000s	165440.051us	49	50	98.00
Idlecsbactive				50	50	100.00
	spi_host_idlecsbactive	20.000s	1680.521us	50	50	100.00
data_fifo_status				50	50	100.00
	spi_host_overflow_underflow	41.000s	2050.517us	50	50	100.00
alert_test				50	50	100.00
	spi_host_alert_test	2.000s	26.009us	50	50	100.00
intr_test				50	50	100.00
	spi_host_intr_test	2.000s	17.217us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_host_tl_errors	3.000s	87.565us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_host_tl_errors	3.000s	87.565us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	20.673us	5	5	100.00
	spi_host_csr_rw	2.000s	19.637us	20	20	100.00
	spi_host_csr_aliasing	2.000s	68.027us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	29.594us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	20.673us	5	5	100.00
	spi_host_csr_rw	2.000s	19.637us	20	20	100.00
	spi_host_csr_aliasing	2.000s	68.027us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	29.594us	20	20	100.00

V2S

25/25 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_host_sec_cm	2.000s	44.952us	5	5	100.00
	spi_host_tl_intg_err	2.000s	59.865us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_host_tl_intg_err	2.000s	59.865us	20	20	100.00

unmapped

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				10	10	100.00
	spi_host_upper_range_clkdiv	543.000s	45986.641us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [] vs []) Regname: spi_host_reg_block.status.rxfull reset value:
	spi_host_status_stall	374131303501385814867393201338504986133518491496355586147532819154429790527	4214	UVM_ERROR @ 2438273448 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0 UVM_INFO @ 2438273448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [spi_host_smoke_vseq] wait timeout occurred!
	spi_host_stress_all	12199047846112194670433687886829726225384321534778990748190797662268672826057	83	UVM_FATAL @ 10021882500 ps: (cip_base_vseq.sv:454) [uvm_test_top.env.virtual_sequencer.spi_host_smoke_vseq] wait timeout occurred! UVM_INFO @ 10021882500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (spi_host_scoreboard.sv:220) scoreboard [scoreboard] 'rx_data_q.size' is empty - hence can't compare TXN
	spi_host_spien	27762211175781369941679319023103683948441141972922795860942476224785565831805	194	UVM_FATAL @ 75125685 ps: (spi_host_scoreboard.sv:220) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] 'rx_data_q.size' is empty - hence can't compare TXN UVM_INFO @ 75125685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	spi_host_stress_all	52977895938181261827482454893324756893269662778045581477429890739775093109707	189	UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = ns spi_host_reg_block.status.active (addr=, Comparison=CompareOpEq, exp_data=, call_count=
	spi_host_stress_all	18347180614075956803394874676852935689376210636091891058162330828318834926179	213	UVM_FATAL @ 26416640507 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 15000000ns spi_host_reg_block.status.active (addr=0x79aea14, Comparison=CompareOpEq, exp_data=0x0, call_count=31 UVM_INFO @ 26416640507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---