Simulation Results: sram_ctrl/main

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.67 %
  • code
  • 96.96 %
  • assert
  • 96.46 %
  • func
  • 96.60 %
  • block
  • 96.35 %
  • line
  • 97.11 %
  • branch
  • 94.65 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 11.000s 2766.684us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.000s 20.180us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 17.831us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.000s 141.876us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 37.047us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 370.599us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 17.831us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 37.047us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 264.000s 13846.125us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 159.000s 10874.723us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 56.000s 66574.629us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 276.000s 12383.301us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 188.000s 39574.546us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 80.000s 11855.482us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 68.000s 35339.169us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 38.000s 6868.924us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 8.000s 2570.471us 5 5 100.00
sram_ctrl_partial_access_b2b 264.000s 14984.259us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 8.000s 688.694us 5 5 100.00
sram_ctrl_throughput_w_partial_write 10.000s 2573.696us 5 5 100.00
sram_ctrl_throughput_w_readback 9.000s 669.957us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 20.000s 7323.861us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 7.000s 2585.925us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 440.000s 74810.036us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 24.654us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 317.760us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 317.760us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.000s 20.180us 5 5 100.00
sram_ctrl_csr_rw 2.000s 17.831us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 37.047us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 65.027us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.000s 20.180us 5 5 100.00
sram_ctrl_csr_rw 2.000s 17.831us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 37.047us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 65.027us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 36.000s 39172.155us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 7.000s 6985.720us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 557.487us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 7.000s 6985.720us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 557.487us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 20.000s 7323.861us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 20.000s 7323.861us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 17.831us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 38.000s 6868.924us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 38.000s 6868.924us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 38.000s 6868.924us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 68.000s 35339.169us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 8.000s 1394.795us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 36.000s 39172.155us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 7.000s 702.353us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 11.000s 2766.684us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 11.000s 2766.684us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 38.000s 6868.924us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 7.000s 6985.720us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 68.000s 35339.169us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 7.000s 6985.720us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 7.000s 6985.720us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 11.000s 2766.684us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 7.000s 6985.720us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 83.000s 9175.181us 5 5 100.00