Simulation Results: sram_ctrl/ret

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.15 %
  • code
  • 83.42 %
  • assert
  • 96.43 %
  • func
  • 96.60 %
  • block
  • 93.87 %
  • line
  • 95.04 %
  • branch
  • 89.67 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
95.71%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 3.000s 454.785us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 34.000s 23.348us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 34.000s 28.172us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 35.000s 159.564us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 34.000s 13.867us 5 5 100.00
csr_mem_rw_with_rand_reset 17 20 85.00
sram_ctrl_csr_mem_rw_with_rand_reset 34.000s 55.440us 17 20 85.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 34.000s 28.172us 20 20 100.00
sram_ctrl_csr_aliasing 34.000s 13.867us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 15.000s 8730.388us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 6.000s 335.146us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 13.000s 712.405us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 218.000s 4010.698us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 7.000s 150.839us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 21.000s 2455.459us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 7.000s 505.447us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 14.000s 5329.299us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 3.000s 68.614us 5 5 100.00
sram_ctrl_partial_access_b2b 211.000s 5067.237us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 2.000s 129.741us 5 5 100.00
sram_ctrl_throughput_w_partial_write 2.000s 127.962us 5 5 100.00
sram_ctrl_throughput_w_readback 2.000s 164.301us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 14.000s 192.284us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 41.929us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 48.000s 14899.301us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 42.011us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 35.000s 152.733us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 35.000s 152.733us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 34.000s 23.348us 5 5 100.00
sram_ctrl_csr_rw 34.000s 28.172us 20 20 100.00
sram_ctrl_csr_aliasing 34.000s 13.867us 5 5 100.00
sram_ctrl_same_csr_outstanding 34.000s 26.216us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 34.000s 23.348us 5 5 100.00
sram_ctrl_csr_rw 34.000s 28.172us 20 20 100.00
sram_ctrl_csr_aliasing 34.000s 13.867us 5 5 100.00
sram_ctrl_same_csr_outstanding 34.000s 26.216us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 35.000s 421.933us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_tl_intg_err 35.000s 376.876us 20 20 100.00
sram_ctrl_sec_cm 6.000s 740.117us 5 5 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 6.000s 740.117us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 35.000s 376.876us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 14.000s 192.284us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 14.000s 192.284us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 34.000s 28.172us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 14.000s 5329.299us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 14.000s 5329.299us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 14.000s 5329.299us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 7.000s 505.447us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 35.929us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 35.000s 421.933us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 2.000s 38.255us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 3.000s 454.785us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 3.000s 454.785us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 14.000s 5329.299us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 6.000s 740.117us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 7.000s 505.447us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 6.000s 740.117us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 740.117us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 3.000s 454.785us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 740.117us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 72.000s 3790.293us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 44729654780798080074757582299042544071279116426010026360507188690128688577921 88
UVM_ERROR @ 25205562 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 25205562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_csr_mem_rw_with_rand_reset 2628249272985169259892211354606513560532813297631565278602991156412312167913 88
UVM_ERROR @ 53414618 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (7 [0x7] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 53414618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_csr_mem_rw_with_rand_reset 13981713929564043225823276946858307265243408951974514713686568879838161629510 88
UVM_ERROR @ 94300688 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (2 [0x2] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 94300688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---