Simulation Results: ac_range_check

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
97.89%
V2
97.51%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 20 20 100.00
ac_range_check_smoke 54.000s 5707.010us 20 20 100.00
ac_range_check_smoke_racl 18 20 90.00
ac_range_check_smoke_racl 79.000s 2968.093us 18 20 90.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 3.000s 41.406us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 3.000s 76.650us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 49.000s 2562.214us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 33.000s 1208.034us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 110.271us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 3.000s 76.650us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 1208.034us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 338.243us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 42.000s 5288.437us 1 1 100.00
stress_all 44 50 88.00
ac_range_check_stress_all 302.000s 23995.612us 44 50 88.00
alert_test 50 50 100.00
ac_range_check_alert_test 2.000s 12.995us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 2.000s 24.969us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 5.000s 119.042us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 5.000s 119.042us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 41.406us 5 5 100.00
ac_range_check_csr_rw 3.000s 76.650us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 1208.034us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 370.771us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 41.406us 5 5 100.00
ac_range_check_csr_rw 3.000s 76.650us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 1208.034us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 370.771us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 26.000s 1167.217us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 26.000s 1167.217us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 26.000s 1167.217us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 26.000s 1167.217us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 121.000s 5175.076us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 2.000s 20.586us 5 5 100.00
ac_range_check_tl_intg_err 14.000s 412.746us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 446.000s 2707.180us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 49.000s 1504.686us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_smoke_racl 24022425044986615616979624257819993028983620393950309564060526823890915917459 4130
UVM_ERROR @ 1178657035 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1178657035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 24813656175004735644618002498046038348078006158191838951005497620901802243447 17616
UVM_ERROR @ 7774791941 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 7774791941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 8400327502228528233260715241777726194315059350953145774074892302405491707961 8134
UVM_ERROR @ 985057574 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 985057574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 35284838976679862516234291675718793675702273076491661514299977192350457106038 8950
UVM_ERROR @ 8570287972 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 8570287972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 19767136882203090306699542885789981012201825126402934567824042368098029513079 4232
UVM_ERROR @ 2446252523 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2446252523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 24010159784113103076373327709411127914046571145735847018390575438643158113963 4681
UVM_ERROR @ 1748295166 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1748295166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 71348543785200349851630897829523197126168058214769593146212829483369599736165 13655
UVM_ERROR @ 5982812124 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 5982812124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 110461128352098172025600447497865858561437795331713550901082998767398187662642 20038
UVM_ERROR @ 12881394470 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 12881394470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---