Simulation Results

Simulation Results: csrng

01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.23 %

code
96.23 %

assert
95.85 %

func
90.62 %

block
98.59 %

line
99.57 %

branch
96.46 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		96.94%
V2S		99.85%
V3		0.00%

105/105 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	csrng_smoke	5.000s	246.789us	50	50	100.00
csr_hw_reset				5	5	100.00
	csrng_csr_hw_reset	7.000s	56.027us	5	5	100.00
csr_rw				20	20	100.00
	csrng_csr_rw	8.000s	183.486us	20	20	100.00
csr_bit_bash				5	5	100.00
	csrng_csr_bit_bash	33.000s	2337.895us	5	5	100.00
csr_aliasing				5	5	100.00
	csrng_csr_aliasing	8.000s	70.031us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	csrng_csr_mem_rw_with_rand_reset	7.000s	25.496us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	csrng_csr_rw	8.000s	183.486us	20	20	100.00
	csrng_csr_aliasing	8.000s	70.031us	5	5	100.00

1425/1470 passed

96.94 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	36.000s	1739.177us	500	500	100.00
err				500	500	100.00
	csrng_err	4.000s	119.895us	500	500	100.00
cmds				7	50	14.00
	csrng_cmds	291.000s	21318.758us	7	50	14.00
life cycle				7	50	14.00
	csrng_cmds	291.000s	21318.758us	7	50	14.00
stress_all				48	50	96.00
	csrng_stress_all	548.000s	18987.251us	48	50	96.00
intr_test				50	50	100.00
	csrng_intr_test	7.000s	131.904us	50	50	100.00
alert_test				50	50	100.00
	csrng_alert_test	4.000s	193.368us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	csrng_tl_errors	13.000s	445.964us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	csrng_tl_errors	13.000s	445.964us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	csrng_csr_hw_reset	7.000s	56.027us	5	5	100.00
	csrng_csr_rw	8.000s	183.486us	20	20	100.00
	csrng_csr_aliasing	8.000s	70.031us	5	5	100.00
	csrng_same_csr_outstanding	9.000s	837.111us	20	20	100.00
tl_d_partial_access				50	50	100.00
	csrng_csr_hw_reset	7.000s	56.027us	5	5	100.00
	csrng_csr_rw	8.000s	183.486us	20	20	100.00
	csrng_csr_aliasing	8.000s	70.031us	5	5	100.00
	csrng_same_csr_outstanding	9.000s	837.111us	20	20	100.00

V2S

1343/1345 passed

99.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	csrng_tl_intg_err	16.000s	1514.279us	20	20	100.00
	csrng_sec_cm	5.000s	136.571us	5	5	100.00
sec_cm_config_regwen				70	70	100.00
	csrng_csr_rw	8.000s	183.486us	20	20	100.00
	csrng_regwen	5.000s	209.991us	50	50	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	36.000s	1739.177us	500	500	100.00
sec_cm_intersig_mubi				48	50	96.00
	csrng_stress_all	548.000s	18987.251us	48	50	96.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
	csrng_err	4.000s	119.895us	500	500	100.00
	csrng_sec_cm	5.000s	136.571us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
	csrng_err	4.000s	119.895us	500	500	100.00
	csrng_sec_cm	5.000s	136.571us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
	csrng_err	4.000s	119.895us	500	500	100.00
	csrng_sec_cm	5.000s	136.571us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
	csrng_err	4.000s	119.895us	500	500	100.00
	csrng_sec_cm	5.000s	136.571us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
	csrng_err	4.000s	119.895us	500	500	100.00
	csrng_sec_cm	5.000s	136.571us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	36.000s	1739.177us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
	csrng_err	4.000s	119.895us	500	500	100.00
sec_cm_constants_lc_gated				48	50	96.00
	csrng_stress_all	548.000s	18987.251us	48	50	96.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	36.000s	1739.177us	500	500	100.00
sec_cm_tile_link_bus_integrity				20	20	100.00
	csrng_tl_intg_err	16.000s	1514.279us	20	20	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
	csrng_err	4.000s	119.895us	500	500	100.00
	csrng_sec_cm	5.000s	136.571us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
	csrng_err	4.000s	119.895us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
	csrng_err	4.000s	119.895us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
	csrng_err	4.000s	119.895us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
	csrng_err	4.000s	119.895us	500	500	100.00
	csrng_sec_cm	5.000s	136.571us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	16.000s	917.017us	200	200	100.00
	csrng_err	4.000s	119.895us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	0.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])
	csrng_cmds	9427656078467368869880264064615087847534183093089324392240793356924003280676	130	UVM_FATAL @ 937666762 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 229410106927025856637066536797512287108 [0xac96c789e078d351435e0798a00a4384]) UVM_INFO @ 937666762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	83933155643852938240915212701523508259528748536156028409878614720961066688149	130	UVM_FATAL @ 71605489 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 326644850298702406394741122636375733729 [0xf5bd8284adbcae7006ba894133d535e1]) UVM_INFO @ 71605489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	64972056284791314064600250473460321593793183344892793817848714938867187120140	130	UVM_FATAL @ 702674842 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 162514392322077790369998467495852881502 [0x7a43222a37db5d40b9b58f723ff9b65e]) UVM_INFO @ 702674842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	95591986175857668200342287487163863729752529512894457595387547210103932021572	130	UVM_FATAL @ 81497229 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 118876402109368374847925774441865378765 [0x596ec322d6af5d0e0f22ff63f7217bcd]) UVM_INFO @ 81497229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	60307581578241526374073680765335619181930814643906568428262752969951060906474	130	UVM_FATAL @ 169579515 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 194531397274450421813408062888659318444 [0x925962625d844738575989034c42f6ac]) UVM_INFO @ 169579515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	31069621331173522631526263461643937995264391008541180278271351883007268836594	130	UVM_FATAL @ 60222234 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 88499361025717524634972067929610147152 [0x42945b60cdbc90cca028c162cc1e5550]) UVM_INFO @ 60222234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	92882539009256190033850977613215554033610145881135618695083402085301267914044	130	UVM_FATAL @ 93723151 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 126804520507707506863734239361966274490 [0x5f65a98d575a74940d655187ab77f7ba]) UVM_INFO @ 93723151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	84846200200575003455143088330886627008711783575145951657942851638873599747257	130	UVM_FATAL @ 115562555 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 49993700877497817052185853606260389969 [0x259c6fc212b97b4315d644359b503851]) UVM_INFO @ 115562555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	38830346594698923195833565037515719265644814935071283828192755754924765576050	140	UVM_FATAL @ 299704809 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 243013714101068115063480898174741285454 [0xb6d2bd27ca4bdccf9f7cb69f8e128a4e]) UVM_INFO @ 299704809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	61768139136568126652821095393957394970556708667809805860704020076790349760265	130	UVM_FATAL @ 383029171 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 247746354101430487316900315546511739237 [0xba6236529628921c12433a11c7680965]) UVM_INFO @ 383029171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	80658629549296219229600561192528826914173032708868764344882886896057722536174	140	UVM_FATAL @ 300404480 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 276837687430086208988941193880540199446 [0xd044ffcb494651f6095ef3ad704eba16]) UVM_INFO @ 300404480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	105415973472154039058500845735128975338967717134606263735266399904810054590038	130	UVM_FATAL @ 81160526 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 70316518361047372566426151726430718941 [0x34e678053877621cfbbe2fb190ea8bdd]) UVM_INFO @ 81160526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	34883316437319823384837006092103645888172374552205025335005726731173932843697	130	UVM_FATAL @ 15955970 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 179479513419137810391212166084602091208 [0x87067f36ca89c3b6993085903b13d6c8]) UVM_INFO @ 15955970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	65537730372965470905840649095970878579339390769985431347880512633201049312674	130	UVM_FATAL @ 150085186 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 58400323379518981968054335963496310403 [0x2bef7e3f763d6a31a933c3a265f9e683]) UVM_INFO @ 150085186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	41191946201047899151661026753228539145971407188272897998659958269457021221604	130	UVM_FATAL @ 226619423 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 124408310796075642443449591026041451653 [0x5d982b4abee94bc49e263c1bfbb37485]) UVM_INFO @ 226619423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	24588732652645078982233734002021152365649083519948255073810511094500207574843	130	UVM_FATAL @ 402791631 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 84219928167993426402908852782605239724 [0x3f5c2b0c5b24cad5415b079a869785ac]) UVM_INFO @ 402791631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	48182641832579730730780904044533488556799894809796358154409664386048236828345	130	UVM_FATAL @ 55291411 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 20554199190882434788287976658160816538 [0xf769842e0831405f013ad95fa57919a]) UVM_INFO @ 55291411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	109488008508954640907447782304077120707988324681400801132867447163879393612641	130	UVM_FATAL @ 20914560 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 263160010509945051346901573411365169596 [0xc5fac641bdd58c635973a2985b63a9bc]) UVM_INFO @ 20914560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	63197085941543899586945594479920325765395109423478319200366639884903077976114	130	UVM_FATAL @ 32256560 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 102561470930760763685381767071803371348 [0x4d289eecc9ae3adcc39706aac33bef54]) UVM_INFO @ 32256560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	114620911201882031049735076660709857556706817892536185101143287218438626020225	130	UVM_FATAL @ 80682386 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 101565133599819033375886260310197242234 [0x4c68bbb3afe8669ad1409c8c88f1897a]) UVM_INFO @ 80682386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	102929816251775444502590460766753015906015574536633835893182839645252595096687	130	UVM_FATAL @ 241454587 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 217046998144157680194756892170437785075 [0xa349bb36e77035fa3b4c8eb727fff5f3]) UVM_INFO @ 241454587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	25255138314298515055722075146301600936490569874809172019423199992911528273283	130	UVM_FATAL @ 273352111 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 290463527434215358238157009530852719244 [0xda853d92f7936b42375bcc545a8bba8c]) UVM_INFO @ 273352111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	98415471045831218558939358143068141858455783029972188732847252217136532105961	130	UVM_FATAL @ 22890609 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 146296902941744058306600525773009930387 [0x6e0fc234920aafc331bc751ef8814893]) UVM_INFO @ 22890609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	108427731863106912960207950706299882702812149485190763891321006095991580711340	130	UVM_FATAL @ 239538662 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 103987164942541758965016525422900881196 [0x4e3b331116486ac480824c39f079272c]) UVM_INFO @ 239538662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	61238082619641614215993846555346710452044372127235561079843876978874070524124	130	UVM_FATAL @ 31327535 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 234350910969657937778363425096698782319 [0xb04e57fc4531b4af4a3453c995b9626f]) UVM_INFO @ 31327535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	60393918745414728820273687698200723764759678605983628293881920178945468176370	130	UVM_FATAL @ 9252569 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 99499534736013491900441473873711032488 [0x4adae9d0a79ce51fc9ef5dbc519968a8]) UVM_INFO @ 9252569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	86755546657531548327958508229550614097345945126176635103891284294684634799438	130	UVM_FATAL @ 283463136 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 80979989025797605607971518573364011434 [0x3cec2db729b0b8e485e8eb8fed4a61aa]) UVM_INFO @ 283463136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	4117148490963043593272766837641052117954400397517273995670561249278565951713	130	UVM_FATAL @ 27622384 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 219427349491445980306367350222563177962 [0xa5142b98cd15925778bd25e42b11f5ea]) UVM_INFO @ 27622384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	45203896093555910706130186512258415832951048090331427589993025257150548813119	130	UVM_FATAL @ 79075003 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 116314891862925759480630467342192875121 [0x57816eee2bb61aa235b8b4baaac41671]) UVM_INFO @ 79075003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	33446940832675279781562278792265134649752166990468577526885818448287160152064	130	UVM_FATAL @ 67355646 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 233743248014387409163919511187341316103 [0xafd94fe37ca33f33c35e0124edc61007]) UVM_INFO @ 67355646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	39002573637601626142226616982460549829447321860708882103722443141443801949194	130	UVM_FATAL @ 118393700 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 126488576487502046970840467185662960479 [0x5f28d04f2b346fd9cf6a60911e78235f]) UVM_INFO @ 118393700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	108423812202081136581207349532068436188579957018240734220523611271514855232768	130	UVM_FATAL @ 46540744 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 256962611157744940531307253327528117011 [0xc15132e0bbd0ec7fdd15d8189b4ac313]) UVM_INFO @ 46540744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	108601920845501419058233939692152026238397699652055580924773588496080446723154	130	UVM_FATAL @ 106055915 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 135843876838000787859104904595120728708 [0x6632943a6b238a379bb4869ae9e62a84]) UVM_INFO @ 106055915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	110712052831115017298459784413091031248511601299662324431552445819918744270045	130	UVM_FATAL @ 11489362 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 72187507697129284510729332647390563926 [0x364eceeaae83cd3ee97fb2e4b6874e56]) UVM_INFO @ 11489362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	96622007527939283489843496875828330471448367661198230456791938133190885873187	130	UVM_FATAL @ 329104240 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 45803142483021407775550066405890183716 [0x22755d470ed740c9fc8eda757311d224]) UVM_INFO @ 329104240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	37495660287476652518235675583007664999010854065764130593006437428884092487014	130	UVM_FATAL @ 24659950 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 278925576991924247911773008333583861929 [0xd1d71cb27b7694eda7632d3f88eac8a9]) UVM_INFO @ 24659950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	93113139565663549175784112200962271528588077853958726911444551199906647249194	130	UVM_FATAL @ 73344393 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 146350333010040210158715056022737893122 [0x6e1a0c82d7d8a5c6d01762df6cc3b702]) UVM_INFO @ 73344393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	70316818964608267183044975128214415527685980176992156588607887799411075488827	130	UVM_FATAL @ 344524731 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 17000737263039881374833639959482309512 [0xcca390fc9b66989974715c2273b9b88]) UVM_INFO @ 344524731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	10922188042703778404866105038755065436235386202086470645375947353442031396361	130	UVM_FATAL @ 450740392 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 320242810021875279593920360196771831241 [0xf0ec859011eda9edac51ff5c34025dc9]) UVM_INFO @ 450740392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	49037614154459674372214204173494386421639811053061922819128033895201631850485	130	UVM_FATAL @ 74396888 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 174011662781068470413056626997063108713 [0x82e96d5d20b71ac996aee20dfeb8c869]) UVM_INFO @ 74396888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	46419168799418254513300258918046521141511105826744483022246115555459384663721	130	UVM_FATAL @ 18573319 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 11260948877263380792369901325015177726 [0x878c7a5330f0d761c1280e41959d9fe]) UVM_INFO @ 18573319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	21992610934177232122262040543992095225527361944546756704100541572423768568112	130	UVM_FATAL @ 403899653 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 164939007422237983871541162319844220598 [0x7c1618eb38c73194ef7eea05dac01eb6]) UVM_INFO @ 403899653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	csrng_stress_all_with_rand_reset	89763670377312851533791598123521176104957033911781402937468770023811229007838	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	58986989614930568923744270523027388035486920316569546359491036305752770694706	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	62426090707565050122622775603361529251235398929415899530860028805261941900146	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	86527120921667802004704042500135754458613279132064562299694529749258823383964	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	48786069048764004486121430173572123675772971702861692686031594414701257407271	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	6739236536978042353592501886767311554839216066291992861200112710104772304208	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	45943873856536453850847059403011429805354020108090577728266011044455113805037	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	77651479292944835646732654298376593424027954873524929012040700235175563310347	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	36198634695025755226583205917918632861476392228309010474098643252564166364647	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	69088745356700023490957868234271883527963565047122864254326674998012586711820	None	Job timed out after 180 minutes
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits
	csrng_cmds	92090965067991864159730469544706953048375591428485471731498924517090845842669	133	UVM_ERROR @ 315460309 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2897511005 [0xacb4825d] vs 0 [0x0]) reg name: csrng_reg_block.genbits UVM_INFO @ 315460309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq
	csrng_stress_all	153198049947822397329296633561829364275057894906692464222291851144954224123	150	UVM_ERROR @ 3402790832 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq UVM_INFO @ 3402790832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	83224168211023137388922971865667668621507397260116542502834062886831042565306	144	UVM_ERROR @ 1368624079 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq UVM_INFO @ 1368624079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---