Simulation Results: dma

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.52 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 77.38 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 34.000s 1194.617us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 33.000s 1261.813us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 33.000s 358.259us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 3.000s 95.769us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 3.000s 38.794us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 19.000s 1027.872us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 9.000s 879.159us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 7.000s 96.851us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 3.000s 38.794us 20 20 100.00
dma_csr_aliasing 9.000s 879.159us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 145.000s 5658.945us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 313.000s 218402.150us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 1292.000s 429360.358us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 1292.000s 429360.358us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 313.000s 218402.150us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 975.000s 81971.212us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 1292.000s 429360.358us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 51.000s 1464.890us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 354.000s 39408.931us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 14.895us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 3.000s 10.704us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 4.000s 1690.603us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 4.000s 1690.603us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 3.000s 95.769us 5 5 100.00
dma_csr_rw 3.000s 38.794us 20 20 100.00
dma_csr_aliasing 9.000s 879.159us 5 5 100.00
dma_same_csr_outstanding 4.000s 405.770us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 3.000s 95.769us 5 5 100.00
dma_csr_rw 3.000s 38.794us 20 20 100.00
dma_csr_aliasing 9.000s 879.159us 5 5 100.00
dma_same_csr_outstanding 4.000s 405.770us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 37.000s 290.936us 5 5 100.00
dma_generic_stress 975.000s 81971.212us 5 5 100.00
dma_handshake_stress 1292.000s 429360.358us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 34.000s 306.656us 15 15 100.00
tl_intg_err 25 25 100.00
dma_sec_cm 2.000s 10.200us 5 5 100.00
dma_tl_intg_err 6.000s 202.953us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 182.000s 11962.394us 25 25 100.00
dma_longer_transfer 30.000s 105.603us 5 5 100.00
dma_stress_all_with_rand_reset 19.000s 621.946us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 32934729587157911221914775401801839458112886097232795432150303596020256980153 109
UVM_ERROR @ 621946236ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 621946236ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---