Simulation Results: hmac

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.60 %
  • code
  • 98.66 %
  • assert
  • 97.14 %
  • func
  • 100.00 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.85 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 10.150s 16180.928us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.020s 38.395us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 0.990s 134.414us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 8.860s 2926.778us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 6.830s 924.479us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 305.010s 142878.891us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 0.990s 134.414us 20 20 100.00
hmac_csr_aliasing 6.830s 924.479us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 70.540s 22243.287us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 83.060s 1653.146us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 254.360s 80578.067us 30 30 100.00
hmac_test_sha384_vectors 550.420s 32158.221us 75 75 100.00
hmac_test_sha512_vectors 548.550s 25680.431us 75 75 100.00
hmac_test_hmac256_vectors 14.950s 369.966us 50 50 100.00
hmac_test_hmac384_vectors 19.180s 400.386us 60 60 100.00
hmac_test_hmac512_vectors 18.610s 374.187us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 41.950s 13472.096us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1263.340s 17928.421us 10 10 100.00
error 10 10 100.00
hmac_error 80.350s 4382.797us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 125.960s 28105.172us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 10.150s 16180.928us 10 10 100.00
hmac_long_msg 70.540s 22243.287us 10 10 100.00
hmac_back_pressure 83.060s 1653.146us 25 25 100.00
hmac_datapath_stress 1263.340s 17928.421us 10 10 100.00
hmac_burst_wr 41.950s 13472.096us 50 50 100.00
hmac_stress_all 3201.150s 19267.115us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 10.150s 16180.928us 10 10 100.00
hmac_long_msg 70.540s 22243.287us 10 10 100.00
hmac_back_pressure 83.060s 1653.146us 25 25 100.00
hmac_datapath_stress 1263.340s 17928.421us 10 10 100.00
hmac_wipe_secret 125.960s 28105.172us 10 10 100.00
hmac_test_sha256_vectors 254.360s 80578.067us 30 30 100.00
hmac_test_sha384_vectors 550.420s 32158.221us 75 75 100.00
hmac_test_sha512_vectors 548.550s 25680.431us 75 75 100.00
hmac_test_hmac256_vectors 14.950s 369.966us 50 50 100.00
hmac_test_hmac384_vectors 19.180s 400.386us 60 60 100.00
hmac_test_hmac512_vectors 18.610s 374.187us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 10.150s 16180.928us 10 10 100.00
hmac_long_msg 70.540s 22243.287us 10 10 100.00
hmac_back_pressure 83.060s 1653.146us 25 25 100.00
hmac_datapath_stress 1263.340s 17928.421us 10 10 100.00
hmac_burst_wr 41.950s 13472.096us 50 50 100.00
hmac_error 80.350s 4382.797us 10 10 100.00
hmac_wipe_secret 125.960s 28105.172us 10 10 100.00
hmac_test_sha256_vectors 254.360s 80578.067us 30 30 100.00
hmac_test_sha384_vectors 550.420s 32158.221us 75 75 100.00
hmac_test_sha512_vectors 548.550s 25680.431us 75 75 100.00
hmac_test_hmac256_vectors 14.950s 369.966us 50 50 100.00
hmac_test_hmac384_vectors 19.180s 400.386us 60 60 100.00
hmac_test_hmac512_vectors 18.610s 374.187us 75 75 100.00
hmac_stress_all 3201.150s 19267.115us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 3201.150s 19267.115us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.960s 27.082us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.770s 13.848us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 3.870s 228.103us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 3.870s 228.103us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.020s 38.395us 5 5 100.00
hmac_csr_rw 0.990s 134.414us 20 20 100.00
hmac_csr_aliasing 6.830s 924.479us 5 5 100.00
hmac_same_csr_outstanding 2.290s 317.348us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.020s 38.395us 5 5 100.00
hmac_csr_rw 0.990s 134.414us 20 20 100.00
hmac_csr_aliasing 6.830s 924.479us 5 5 100.00
hmac_same_csr_outstanding 2.290s 317.348us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_tl_intg_err 3.730s 1170.829us 20 20 100.00
hmac_sec_cm 1.350s 963.641us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 3.730s 1170.829us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 10.150s 16180.928us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.090s 143.597us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 729.230s 35443.367us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.050s 15.908us 1 1 100.00