Simulation Results: keymgr_dpe

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.30 %
  • code
  • 84.22 %
  • assert
  • 97.64 %
  • func
  • 17.04 %
  • line
  • 97.67 %
  • branch
  • 94.50 %
  • cond
  • 90.12 %
  • toggle
  • 63.15 %
  • FSM
  • 75.68 %
Validation stages
V1
99.05%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
keymgr_dpe_smoke 336.010s 19769.912us 49 50 98.00
csr_hw_reset 5 5 100.00
keymgr_dpe_csr_hw_reset 1.120s 43.484us 5 5 100.00
csr_rw 20 20 100.00
keymgr_dpe_csr_rw 1.580s 95.457us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_dpe_csr_bit_bash 16.880s 10633.575us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_dpe_csr_aliasing 6.770s 933.397us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.980s 146.492us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_dpe_csr_rw 1.580s 95.457us 20 20 100.00
keymgr_dpe_csr_aliasing 6.770s 933.397us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 50 50 100.00
keymgr_dpe_intr_test 1.100s 87.004us 50 50 100.00
alert_test 50 50 100.00
keymgr_dpe_alert_test 1.500s 38.909us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_dpe_tl_errors 5.600s 203.404us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_dpe_tl_errors 5.600s 203.404us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_dpe_csr_hw_reset 1.120s 43.484us 5 5 100.00
keymgr_dpe_csr_rw 1.580s 95.457us 20 20 100.00
keymgr_dpe_csr_aliasing 6.770s 933.397us 5 5 100.00
keymgr_dpe_same_csr_outstanding 3.840s 90.874us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_dpe_csr_hw_reset 1.120s 43.484us 5 5 100.00
keymgr_dpe_csr_rw 1.580s 95.457us 20 20 100.00
keymgr_dpe_csr_aliasing 6.770s 933.397us 5 5 100.00
keymgr_dpe_same_csr_outstanding 3.840s 90.874us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
keymgr_dpe_tl_intg_err 6.190s 1000.141us 20 20 100.00
keymgr_dpe_sec_cm 18.150s 6026.609us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.230s 179.431us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.230s 179.431us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.230s 179.431us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.230s 179.431us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 7.040s 1157.727us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 18.150s 6026.609us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 18.150s 6026.609us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_dpe_smoke 95840655502194205524919642081292496250237253934071516425522221586908230815363 145
UVM_ERROR @ 6115528 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 6115528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---