Simulation Results: kmac/masked

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.83 %
  • code
  • 94.53 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 81.69 %
Validation stages
V1
99.13%
V2
100.00%
V2S
99.56%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
kmac_smoke 104.500s 16965.067us 49 50 98.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 0.970s 118.483us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.180s 78.672us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 14.860s 5996.661us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.190s 406.495us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.090s 226.362us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.180s 78.672us 20 20 100.00
kmac_csr_aliasing 6.190s 406.495us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.890s 15.475us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.190s 130.150us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3900.790s 198523.319us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1233.960s 15609.728us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1786.260s 68944.670us 5 5 100.00
kmac_test_vectors_sha3_256 1462.990s 18245.330us 5 5 100.00
kmac_test_vectors_sha3_384 1643.540s 235780.540us 5 5 100.00
kmac_test_vectors_sha3_512 1187.380s 51599.618us 5 5 100.00
kmac_test_vectors_shake_128 2496.440s 375563.487us 5 5 100.00
kmac_test_vectors_shake_256 638.920s 141136.202us 5 5 100.00
kmac_test_vectors_kmac 3.530s 929.462us 5 5 100.00
kmac_test_vectors_kmac_xof 3.760s 122.571us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 446.850s 14816.797us 50 50 100.00
app 50 50 100.00
kmac_app 399.550s 28089.202us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 376.560s 68427.038us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 471.060s 288657.465us 50 50 100.00
error 50 50 100.00
kmac_error 575.070s 87260.267us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 21.020s 7712.845us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.730s 137.547us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 44.310s 5633.464us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 8.970s 2111.525us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 51.490s 6598.597us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 43.190s 982.957us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3183.680s 93339.932us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 0.950s 29.385us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.400s 59.745us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.160s 236.940us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.160s 236.940us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 0.970s 118.483us 5 5 100.00
kmac_csr_rw 1.180s 78.672us 20 20 100.00
kmac_csr_aliasing 6.190s 406.495us 5 5 100.00
kmac_same_csr_outstanding 1.960s 219.769us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 0.970s 118.483us 5 5 100.00
kmac_csr_rw 1.180s 78.672us 20 20 100.00
kmac_csr_aliasing 6.190s 406.495us 5 5 100.00
kmac_same_csr_outstanding 1.960s 219.769us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.080s 158.683us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.080s 158.683us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.080s 158.683us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.080s 158.683us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 3.850s 240.362us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.240s 1299.817us 20 20 100.00
kmac_sec_cm 91.740s 5100.938us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.240s 1299.817us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 43.190s 982.957us 50 50 100.00
sec_cm_sw_key_key_masking 49 50 98.00
kmac_smoke 104.500s 16965.067us 49 50 98.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 446.850s 14816.797us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.080s 158.683us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 91.740s 5100.938us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 91.740s 5100.938us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 91.740s 5100.938us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 49 50 98.00
kmac_smoke 104.500s 16965.067us 49 50 98.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 43.190s 982.957us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 91.740s 5100.938us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 434.370s 74587.093us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 49 50 98.00
kmac_smoke 104.500s 16965.067us 49 50 98.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 298.220s 4116.094us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 99311773390243306138367029054351271979496019628561815618199444170469945167503 483
UVM_ERROR @ 19920868518 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 19920868518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 107109791760629497440753503927564513863771339284532501514032060421404291518844 240
UVM_ERROR @ 10491497767 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 10491497767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_smoke 6282710172687939423432450429876228262252324080889174083815546626046989731584 77
UVM_ERROR @ 147467600 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 147467600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---