Simulation Results: lc_ctrl/volatile_unlock_enabled

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.84 %
  • code
  • 89.32 %
  • assert
  • 95.99 %
  • func
  • 96.22 %
  • line
  • 97.87 %
  • branch
  • 96.85 %
  • cond
  • 82.35 %
  • toggle
  • 91.35 %
  • FSM
  • 78.18 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
V3
44.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 7.450s 188.542us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.390s 23.802us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.340s 47.397us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 3.100s 102.903us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.580s 83.805us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.950s 75.457us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.340s 47.397us 20 20 100.00
lc_ctrl_csr_aliasing 1.580s 83.805us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 8.200s 1089.269us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.130s 4326.865us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.370s 14.483us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.560s 214.473us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 16.250s 388.957us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 17.380s 3146.326us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 16.250s 388.957us 50 50 100.00
lc_ctrl_prog_failure 4.560s 214.473us 50 50 100.00
lc_ctrl_errors 17.380s 3146.326us 50 50 100.00
lc_ctrl_security_escalation 12.990s 798.649us 50 50 100.00
lc_ctrl_jtag_state_failure 88.250s 17836.641us 20 20 100.00
lc_ctrl_jtag_prog_failure 25.180s 4876.624us 20 20 100.00
lc_ctrl_jtag_errors 70.830s 7193.285us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_csr_hw_reset 4.670s 238.144us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.840s 363.692us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 37.880s 2390.644us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 22.550s 4894.213us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.690s 26.297us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.410s 987.025us 10 10 100.00
lc_ctrl_jtag_alert_test 1.850s 33.753us 10 10 100.00
lc_ctrl_jtag_smoke 14.610s 2607.527us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.290s 746.306us 20 20 100.00
lc_ctrl_jtag_prog_failure 25.180s 4876.624us 20 20 100.00
lc_ctrl_jtag_errors 70.830s 7193.285us 20 20 100.00
lc_ctrl_jtag_access 18.890s 19114.935us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 28.690s 2473.749us 10 10 100.00
jtag_priority 8 10 80.00
lc_ctrl_jtag_priority 39.960s 10004.644us 8 10 80.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.640s 42.287us 50 50 100.00
stress_all 48 50 96.00
lc_ctrl_stress_all 234.580s 23288.744us 48 50 96.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.650s 23.784us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.960s 1030.353us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.960s 1030.353us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.390s 23.802us 5 5 100.00
lc_ctrl_csr_rw 1.340s 47.397us 20 20 100.00
lc_ctrl_csr_aliasing 1.580s 83.805us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.320s 147.454us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.390s 23.802us 5 5 100.00
lc_ctrl_csr_rw 1.340s 47.397us 20 20 100.00
lc_ctrl_csr_aliasing 1.580s 83.805us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.320s 147.454us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 2.820s 755.836us 20 20 100.00
lc_ctrl_sec_cm 13.980s 1587.060us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 2.820s 755.836us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.130s 4326.865us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 16.250s 388.957us 50 50 100.00
lc_ctrl_sec_cm 13.980s 1587.060us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 16.250s 388.957us 50 50 100.00
lc_ctrl_sec_cm 13.980s 1587.060us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 16.250s 388.957us 50 50 100.00
lc_ctrl_sec_cm 13.980s 1587.060us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 16.250s 388.957us 50 50 100.00
lc_ctrl_sec_cm 13.980s 1587.060us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 16.250s 388.957us 50 50 100.00
lc_ctrl_sec_cm 13.980s 1587.060us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 16.250s 388.957us 50 50 100.00
lc_ctrl_sec_cm 13.980s 1587.060us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 16.250s 388.957us 50 50 100.00
lc_ctrl_sec_cm 13.980s 1587.060us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 16.250s 388.957us 50 50 100.00
lc_ctrl_sec_cm 13.980s 1587.060us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 12.990s 798.649us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 8.200s 1089.269us 50 50 100.00
lc_ctrl_jtag_state_post_trans 22.290s 746.306us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 14.160s 1737.403us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 14.160s 1737.403us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 17.320s 4262.415us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 16.980s 1587.628us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 16.980s 1587.628us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 22 50 44.00
lc_ctrl_stress_all_with_rand_reset 169.530s 5629.064us 22 50 44.00

Error Messages

   Test seed line log context
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred!
lc_ctrl_jtag_priority 102866962824297159579422608323812964368595836732883678469195752114996240942653 148
UVM_FATAL @ 10012623595 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
UVM_INFO @ 10012623595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_priority 94327030159250225632288348958270220304803214778156998732431662931230738104792 148
UVM_FATAL @ 10004644009 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
UVM_INFO @ 10004644009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 73624115166109035615128556231134435700577833852638349097752577413415165125722 7888
UVM_ERROR @ 2592025117 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2592025117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75168388324622421591872967535730699322472255509691530982065122672370497098280 1016
UVM_ERROR @ 3687894616 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3687894616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 52800183301660610010141598619327912738013692119935307730919922604303538000237 4195
UVM_ERROR @ 24911004330 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 24911004330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 44764268923834695972794123922941591285047816815542257869691927958956857967239 5074
UVM_ERROR @ 783930902 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 783930902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 80398774548112472737842751633654643835712903883504493775677221417659179510023 14024
UVM_ERROR @ 4394059451 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4394059451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 66149356887280030840524495708335911411148192648750540533187862743086380123744 4144
UVM_ERROR @ 2649482806 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2649482806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13891203696379278084907564218023059898736639164104610362614525929559801028926 2032
UVM_ERROR @ 7280850897 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7280850897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 12778940325220987337589204676748232997910102234857669228672416703025935524718 1087
UVM_ERROR @ 767383434 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 767383434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14986867626975625815219806185769948830496179437924880569073664501376554825210 5039
UVM_ERROR @ 2046224457 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2046224457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34081445285208933865181308304834490947991565552208408566049282484410786955103 1805
UVM_ERROR @ 1246248118 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1246248118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 78141963444585251542260124615827145613306689551389592755414580013475658398566 12425
UVM_ERROR @ 19240039488 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 19240039488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 7518703622349539977620951750284889316516116376572453979774600411222243042219 9674
UVM_ERROR @ 9589320765 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9589320765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65074342553030055157558181029707064505442299466368538857205547360936551562609 434
UVM_ERROR @ 4309692301 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4309692301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13063604275773333994422581576721786135327600702040285096695844859578052727340 1094
UVM_ERROR @ 6282194762 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6282194762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 72305224211735256155871077729113463170611691873875260882687821655691292475953 496
UVM_ERROR @ 1021111824 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10019 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1021111824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 112040811068007092989922892990906859242002565193675072121869264919832270174626 3975
UVM_ERROR @ 3407293316 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3407293316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34780199072853023593332926581481498286673187131818114119878084542814102983034 8078
UVM_ERROR @ 5610730165 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5610730165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 23720585348539093923461311408822908106938480122571753846409833416138956872964 1437
UVM_ERROR @ 5350077177 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5350077177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 89716698115957970381799864806977037928267902174794379198136322930575078589024 6155
UVM_ERROR @ 6144571413 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6144571413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 48906137254232935188293419099965184283293477812005015747735658433087888288538 616
UVM_ERROR @ 2891878882 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2891878882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 33648672004099861111225916197928826128174951288372293162581998645420931274661 3908
UVM_ERROR @ 10007693235 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10007693235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 33982001307544897883319761140883820283086035488634781230681802632686327573095 6123
UVM_ERROR @ 3124429408 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3124429408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 39509242927851269373367687263499136664117507429953949897476517267069897923992 5853
UVM_ERROR @ 53291002410 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 53291002410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 95104358007969337119962413277809854674776888329893515365403651546576420992563 5127
UVM_ERROR @ 27861442440 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 27861442440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 44686689341972453690343199894811620447233963471524998585839057945500459645316 176
UVM_ERROR @ 1319909273 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1319909273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81940620968002664079222619815020030561894880329413254448024427921338526668305 304
UVM_ERROR @ 992781454 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 992781454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 88066598659611169815203361188267146468592469752367083742857534139843038704369 5371
UVM_ERROR @ 4897621015 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 4897621015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 26665785807629681494318333218541211365112798003677602555548899503405433629470 9547
UVM_ERROR @ 2509219519 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 2509219519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:*
lc_ctrl_stress_all 25513703316663777370978603456598524984732320213896216817835935013660685454727 9615
UVM_ERROR @ 4615900655 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 4615900655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all 10114801113390690947312342221801525660537830286897090163375829037914808151466 6426
UVM_ERROR @ 15689727749 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 15689727749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---