Simulation Results: rom_ctrl/32kb

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.65%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.340s 589.956us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 9.260s 187.842us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 7.860s 2001.231us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 7.800s 8209.060us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 5.720s 171.389us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.400s 332.767us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 7.860s 2001.231us 20 20 100.00
rom_ctrl_csr_aliasing 5.720s 171.389us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 6.300s 166.806us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 6.680s 172.818us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.710s 181.310us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 36.240s 5572.154us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 9.550s 1041.566us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 8.940s 2281.978us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 10.260s 516.209us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 10.260s 516.209us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.260s 187.842us 5 5 100.00
rom_ctrl_csr_rw 7.860s 2001.231us 20 20 100.00
rom_ctrl_csr_aliasing 5.720s 171.389us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.660s 559.649us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.260s 187.842us 5 5 100.00
rom_ctrl_csr_rw 7.860s 2001.231us 20 20 100.00
rom_ctrl_csr_aliasing 5.720s 171.389us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.660s 559.649us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.460s 11355.793us 17 20 85.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.360s 856.086us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 258.050s 955.133us 5 5 100.00
rom_ctrl_tl_intg_err 65.890s 837.339us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 258.050s 955.133us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 258.050s 955.133us 5 5 100.00
sec_cm_checker_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.460s 11355.793us 17 20 85.00
sec_cm_checker_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.460s 11355.793us 17 20 85.00
sec_cm_checker_fsm_local_esc 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.460s 11355.793us 17 20 85.00
sec_cm_compare_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.460s 11355.793us 17 20 85.00
sec_cm_compare_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.460s 11355.793us 17 20 85.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 258.050s 955.133us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 258.050s 955.133us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.340s 589.956us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.340s 589.956us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.340s 589.956us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 65.890s 837.339us 20 20 100.00
sec_cm_bus_local_esc 19 22 86.36
rom_ctrl_corrupt_sig_fatal_chk 136.460s 11355.793us 17 20 85.00
rom_ctrl_kmac_err_chk 9.550s 1041.566us 2 2 100.00
sec_cm_mux_mubi 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.460s 11355.793us 17 20 85.00
sec_cm_mux_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.460s 11355.793us 17 20 85.00
sec_cm_ctrl_redun 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.460s 11355.793us 17 20 85.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.360s 856.086us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 258.050s 955.133us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 349.600s 19176.622us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 70253850101263654649592248423961989042042359839538651058077359673444820422976 90
UVM_ERROR @ 1249373556 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1249373556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 64342698184824773455373744648003642896547867141989793443948147228239194888270 86
UVM_ERROR @ 451920597 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 451920597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 101153984535750243901759362188972927211664427743943624859271785706362199918528 82
UVM_ERROR @ 321744733 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 321744733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---