Simulation Results: rom_ctrl/64kb

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.51 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.05 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
95.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 12.520s 1099.335us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 17.770s 380.347us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 12.010s 334.668us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 10.010s 703.055us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 10.700s 1156.953us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.940s 228.055us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 12.010s 334.668us 20 20 100.00
rom_ctrl_csr_aliasing 10.700s 1156.953us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 10.060s 211.420us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 12.040s 290.619us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 12.170s 312.249us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 50.630s 2736.647us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 17.280s 2023.889us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 15.660s 3671.684us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 20.940s 2023.631us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 20.940s 2023.631us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 17.770s 380.347us 5 5 100.00
rom_ctrl_csr_rw 12.010s 334.668us 20 20 100.00
rom_ctrl_csr_aliasing 10.700s 1156.953us 5 5 100.00
rom_ctrl_same_csr_outstanding 16.250s 313.841us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 17.770s 380.347us 5 5 100.00
rom_ctrl_csr_rw 12.010s 334.668us 20 20 100.00
rom_ctrl_csr_aliasing 10.700s 1156.953us 5 5 100.00
rom_ctrl_same_csr_outstanding 16.250s 313.841us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.940s 24873.643us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 59.530s 15238.965us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 547.230s 566.235us 5 5 100.00
rom_ctrl_tl_intg_err 141.880s 1535.541us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 547.230s 566.235us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 547.230s 566.235us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.940s 24873.643us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.940s 24873.643us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.940s 24873.643us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.940s 24873.643us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.940s 24873.643us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 547.230s 566.235us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 547.230s 566.235us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 12.520s 1099.335us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 12.520s 1099.335us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 12.520s 1099.335us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 141.880s 1535.541us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.940s 24873.643us 20 20 100.00
rom_ctrl_kmac_err_chk 17.280s 2023.889us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.940s 24873.643us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.940s 24873.643us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.940s 24873.643us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 59.530s 15238.965us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 547.230s 566.235us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 20 95.00
rom_ctrl_stress_all_with_rand_reset 260.220s 5720.716us 19 20 95.00

Error Messages

   Test seed line log context
UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
rom_ctrl_stress_all_with_rand_reset 27855323059462858654343466082144364686942722700949723611157592169690173708951 124
UVM_FATAL @ 2464157862 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 2464157862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---