| V1 |
|
98.89% |
| V2 |
|
54.06% |
| V2S |
|
95.56% |
| V3 |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 2 | 2 | 100.00 | |||
| rv_dm_smoke | 2.970s | 1214.094us | 2 | 2 | 100.00 | |
| jtag_dtm_csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_dm_jtag_dtm_csr_hw_reset | 2.270s | 877.639us | 5 | 5 | 100.00 | |
| jtag_dtm_csr_rw | 20 | 20 | 100.00 | |||
| rv_dm_jtag_dtm_csr_rw | 2.700s | 812.183us | 20 | 20 | 100.00 | |
| jtag_dtm_csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_dm_jtag_dtm_csr_bit_bash | 78.380s | 36315.967us | 5 | 5 | 100.00 | |
| jtag_dtm_csr_aliasing | 5 | 5 | 100.00 | |||
| rv_dm_jtag_dtm_csr_aliasing | 4.770s | 1160.476us | 5 | 5 | 100.00 | |
| jtag_dmi_csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_dm_jtag_dmi_csr_hw_reset | 14.080s | 5579.989us | 5 | 5 | 100.00 | |
| jtag_dmi_csr_rw | 20 | 20 | 100.00 | |||
| rv_dm_jtag_dmi_csr_rw | 28.460s | 17263.073us | 20 | 20 | 100.00 | |
| jtag_dmi_csr_bit_bash | 20 | 20 | 100.00 | |||
| rv_dm_jtag_dmi_csr_bit_bash | 109.800s | 109005.611us | 20 | 20 | 100.00 | |
| jtag_dmi_csr_aliasing | 5 | 5 | 100.00 | |||
| rv_dm_jtag_dmi_csr_aliasing | 84.680s | 254977.635us | 5 | 5 | 100.00 | |
| jtag_dmi_cmderr_busy | 2 | 2 | 100.00 | |||
| rv_dm_cmderr_busy | 1.590s | 935.754us | 2 | 2 | 100.00 | |
| jtag_dmi_cmderr_not_supported | 2 | 2 | 100.00 | |||
| rv_dm_cmderr_not_supported | 2.120s | 305.785us | 2 | 2 | 100.00 | |
| cmderr_exception | 2 | 2 | 100.00 | |||
| rv_dm_cmderr_exception | 2.210s | 801.676us | 2 | 2 | 100.00 | |
| mem_tl_access_resuming | 0 | 2 | 0.00 | |||
| rv_dm_mem_tl_access_resuming | 1.610s | 195.874us | 0 | 2 | 0.00 | |
| mem_tl_access_halted | 2 | 2 | 100.00 | |||
| rv_dm_mem_tl_access_halted | 2.010s | 340.072us | 2 | 2 | 100.00 | |
| cmderr_halt_resume | 2 | 2 | 100.00 | |||
| rv_dm_cmderr_halt_resume | 1.580s | 916.105us | 2 | 2 | 100.00 | |
| dataaddr_rw_access | 2 | 2 | 100.00 | |||
| rv_dm_dataaddr_rw_access | 1.130s | 99.932us | 2 | 2 | 100.00 | |
| halt_resume | 8 | 8 | 100.00 | |||
| rv_dm_halt_resume_whereto | 2.970s | 1078.499us | 8 | 8 | 100.00 | |
| progbuf_busy | 2 | 2 | 100.00 | |||
| rv_dm_cmderr_busy | 1.590s | 935.754us | 2 | 2 | 100.00 | |
| abstractcmd_status | 2 | 2 | 100.00 | |||
| rv_dm_abstractcmd_status | 1.540s | 351.171us | 2 | 2 | 100.00 | |
| progbuf_read_write_execute | 2 | 2 | 100.00 | |||
| rv_dm_progbuf_read_write_execute | 1.160s | 185.345us | 2 | 2 | 100.00 | |
| progbuf_exception | 2 | 2 | 100.00 | |||
| rv_dm_cmderr_exception | 2.210s | 801.676us | 2 | 2 | 100.00 | |
| rom_read_access | 2 | 2 | 100.00 | |||
| rv_dm_rom_read_access | 0.950s | 135.458us | 2 | 2 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_dm_csr_hw_reset | 2.680s | 268.067us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_dm_csr_rw | 2.930s | 256.868us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_dm_csr_bit_bash | 65.670s | 10258.671us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_dm_csr_aliasing | 69.130s | 13691.753us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_dm_csr_mem_rw_with_rand_reset | 4.290s | 363.529us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_dm_csr_aliasing | 69.130s | 13691.753us | 5 | 5 | 100.00 | |
| rv_dm_csr_rw | 2.930s | 256.868us | 20 | 20 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| rv_dm_mem_walk | 1.670s | 191.272us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| rv_dm_mem_partial_access | 1.370s | 173.667us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| idcode | 2 | 2 | 100.00 | |||
| rv_dm_smoke | 2.970s | 1214.094us | 2 | 2 | 100.00 | |
| jtag_dtm_hard_reset | 2 | 2 | 100.00 | |||
| rv_dm_jtag_dtm_hard_reset | 1.140s | 364.840us | 2 | 2 | 100.00 | |
| jtag_dtm_idle_hint | 2 | 2 | 100.00 | |||
| rv_dm_jtag_dtm_idle_hint | 1.250s | 169.448us | 2 | 2 | 100.00 | |
| jtag_dmi_failed_op | 2 | 2 | 100.00 | |||
| rv_dm_dmi_failed_op | 1.930s | 540.847us | 2 | 2 | 100.00 | |
| jtag_dmi_dm_inactive | 2 | 2 | 100.00 | |||
| rv_dm_jtag_dmi_dm_inactive | 2.940s | 898.671us | 2 | 2 | 100.00 | |
| sba | 0 | 40 | 0.00 | |||
| rv_dm_sba_tl_access | 14.480s | 17294.374us | 0 | 20 | 0.00 | |
| rv_dm_delayed_resp_sba_tl_access | 10.080s | 7849.974us | 0 | 20 | 0.00 | |
| bad_sba | 0 | 20 | 0.00 | |||
| rv_dm_bad_sba_tl_access | 13.870s | 5564.283us | 0 | 20 | 0.00 | |
| sba_autoincrement | 4 | 20 | 20.00 | |||
| rv_dm_autoincr_sba_tl_access | 123.790s | 122460.696us | 4 | 20 | 20.00 | |
| jtag_dmi_debug_disabled | 0 | 2 | 0.00 | |||
| rv_dm_jtag_dmi_debug_disabled | 1.290s | 81.035us | 0 | 2 | 0.00 | |
| sba_debug_disabled | 2 | 2 | 100.00 | |||
| rv_dm_sba_debug_disabled | 6.460s | 2935.957us | 2 | 2 | 100.00 | |
| ndmreset_req | 2 | 2 | 100.00 | |||
| rv_dm_ndmreset_req | 1.370s | 712.505us | 2 | 2 | 100.00 | |
| hart_unavail | 0 | 5 | 0.00 | |||
| rv_dm_hart_unavail | 1.900s | 270.194us | 0 | 5 | 0.00 | |
| tap_ctrl_transitions | 11 | 11 | 100.00 | |||
| rv_dm_tap_fsm_rand_reset | 82.870s | 4295.200us | 10 | 10 | 100.00 | |
| rv_dm_tap_fsm | 6.350s | 8582.575us | 1 | 1 | 100.00 | |
| hartsel_warl | 1 | 1 | 100.00 | |||
| rv_dm_hartsel_warl | 1.070s | 152.561us | 1 | 1 | 100.00 | |
| stress_all | 3 | 50 | 6.00 | |||
| rv_dm_stress_all | 9134.670s | 10000000.000us | 3 | 50 | 6.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_dm_alert_test | 1.440s | 142.587us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_dm_tl_errors | 6.770s | 1924.499us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_dm_tl_errors | 6.770s | 1924.499us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_dm_csr_aliasing | 69.130s | 13691.753us | 5 | 5 | 100.00 | |
| rv_dm_csr_hw_reset | 2.680s | 268.067us | 5 | 5 | 100.00 | |
| rv_dm_csr_rw | 2.930s | 256.868us | 20 | 20 | 100.00 | |
| rv_dm_same_csr_outstanding | 8.340s | 2792.459us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_dm_csr_aliasing | 69.130s | 13691.753us | 5 | 5 | 100.00 | |
| rv_dm_csr_hw_reset | 2.680s | 268.067us | 5 | 5 | 100.00 | |
| rv_dm_csr_rw | 2.930s | 256.868us | 20 | 20 | 100.00 | |
| rv_dm_same_csr_outstanding | 8.340s | 2792.459us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_dm_tl_intg_err | 29.540s | 2587.976us | 20 | 20 | 100.00 | |
| rv_dm_sec_cm | 2.420s | 429.670us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_dm_tl_intg_err | 29.540s | 2587.976us | 20 | 20 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 3 | 4 | 75.00 | |||
| rv_dm_sba_debug_disabled | 6.460s | 2935.957us | 2 | 2 | 100.00 | |
| rv_dm_debug_disabled | 1.550s | 119.225us | 1 | 2 | 50.00 | |
| sec_cm_lc_dft_en_intersig_mubi | 3 | 4 | 75.00 | |||
| rv_dm_sba_debug_disabled | 6.460s | 2935.957us | 2 | 2 | 100.00 | |
| rv_dm_debug_disabled | 1.550s | 119.225us | 1 | 2 | 50.00 | |
| sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 2 | 2 | 100.00 | |||
| rv_dm_smoke | 2.970s | 1214.094us | 2 | 2 | 100.00 | |
| sec_cm_dm_en_ctrl_lc_gated | 9 | 10 | 90.00 | |||
| rv_dm_buffered_enable | 2.430s | 353.437us | 9 | 10 | 90.00 | |
| sec_cm_sba_tl_lc_gate_fsm_sparse | 4 | 4 | 100.00 | |||
| rv_dm_sparse_lc_gate_fsm | 1.130s | 58.678us | 4 | 4 | 100.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 4 | 4 | 100.00 | |||
| rv_dm_sparse_lc_gate_fsm | 1.130s | 58.678us | 4 | 4 | 100.00 | |
| sec_cm_exec_ctrl_mubi | 9 | 10 | 90.00 | |||
| rv_dm_buffered_enable | 2.430s | 353.437us | 9 | 10 | 90.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| rv_dm_stress_all_with_rand_reset | 21.820s | 913.735us | 0 | 10 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| rv_dm_scanmode | 155.280s | 300000.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared: | ||||
| rv_dm_sba_tl_access | 29078913480980160838074458110588708004191511876075455471444146148166559219388 | 86 |
UVM_ERROR @ 6111317531 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5519
|
|
| rv_dm_autoincr_sba_tl_access | 57875339056877769882184437705418387905118580960803699815940579634771970430262 | 86 |
UVM_ERROR @ 8388385687 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5409
|
|
| rv_dm_sba_tl_access | 55236103897645772336639108173764129432449368747248740344346089661493653240365 | 86 |
UVM_ERROR @ 3440487516 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5427
|
|
| rv_dm_sba_tl_access | 41634903142947426483276628202427332870731087238715384416749856840521382713542 | 86 |
UVM_ERROR @ 1030428825 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5377
|
|
| rv_dm_bad_sba_tl_access | 11414366391814331396645109536610975732212906473108488723697012717620989173587 | 86 |
UVM_ERROR @ 3262893569 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5399
|
|
| rv_dm_sba_tl_access | 72786861270772882067977820268213847699995507477770616609381548437861344135693 | 86 |
UVM_ERROR @ 10663368621 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5347
|
|
| rv_dm_sba_tl_access | 101870560780502854363469220040463037576484167182871896705193398417942366076654 | 86 |
UVM_ERROR @ 17294373787 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5607
|
|
| rv_dm_bad_sba_tl_access | 94068305654144029448550879448697018284479559028067822321400315725203600201809 | 116 |
UVM_ERROR @ 2936078734 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @9693
|
|
| rv_dm_sba_tl_access | 111174533243014580526676721275654126479573324495873756359664141485696150421821 | 86 |
UVM_ERROR @ 1053424821 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5347
|
|
| rv_dm_autoincr_sba_tl_access | 62331421681612915872281610401255095803069124791828870124174521127075058894890 | 128 |
UVM_ERROR @ 46215153556 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @49017
|
|
| rv_dm_sba_tl_access | 50324297754195239438217867340927842001880451993586362146083699605554190012531 | 86 |
UVM_ERROR @ 1859867872 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5347
|
|
| rv_dm_autoincr_sba_tl_access | 74007267697341167177016345113373287011093807654948496776346498612884741869569 | 86 |
UVM_ERROR @ 122460695541 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5511
|
|
| rv_dm_sba_tl_access | 78951984558388648679932628924680410652416499437324474942726257132088112004517 | 86 |
UVM_ERROR @ 5669612061 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5403
|
|
| rv_dm_autoincr_sba_tl_access | 12090352591900721064084919632349169172083751973110047243389533193704263598132 | 86 |
UVM_ERROR @ 20658182477 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5305
|
|
| rv_dm_sba_tl_access | 95054202540555026962385893685583964652422100910964795958015894562661865963842 | 86 |
UVM_ERROR @ 2884605948 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5293
|
|
| rv_dm_sba_tl_access | 84710094709634065145158605139375198547078237843652237089056994875802619721206 | 86 |
UVM_ERROR @ 2607176872 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5423
|
|
| rv_dm_bad_sba_tl_access | 98950332401843692381129338215738417830466662017996417274453378882402936875956 | 86 |
UVM_ERROR @ 11875421962 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5297
|
|
| rv_dm_sba_tl_access | 57069217654677410969681438865088326570086329263211010469032505733813336806438 | 86 |
UVM_ERROR @ 1787363783 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5273
|
|
| rv_dm_bad_sba_tl_access | 8602500537005723521544300180103805773018382735537828650424150465376252658552 | 86 |
UVM_ERROR @ 2981184032 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @6187
|
|
| rv_dm_autoincr_sba_tl_access | 33944630153105723172084198549073838823049407017874552917544446859393237452449 | 161 |
UVM_ERROR @ 9384551650 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23325
|
|
| rv_dm_sba_tl_access | 2111235050964684165448539223920281914098400067964206073454570944622678779876 | 86 |
UVM_ERROR @ 2733702801 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5335
|
|
| rv_dm_bad_sba_tl_access | 35229258453014428626639472608438202350342355976160496951115988626354941796607 | 107 |
UVM_ERROR @ 2035099906 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @9167
|
|
| rv_dm_sba_tl_access | 35830025903045688594255740770680778471883330092891182938635123475329966422795 | 86 |
UVM_ERROR @ 775780271 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5273
|
|
| rv_dm_autoincr_sba_tl_access | 90586107882416541250513099429279965617553837749872086068802147542869332418859 | 86 |
UVM_ERROR @ 25050542771 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5323
|
|
| rv_dm_sba_tl_access | 92495711360805828812444052455339290003851389155713789635442008826751255438583 | 86 |
UVM_ERROR @ 5713755981 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5329
|
|
| rv_dm_delayed_resp_sba_tl_access | 67774418503008783386763680698604789646905528643613575375570332689546531293820 | 86 |
UVM_ERROR @ 2295009388 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5375
|
|
| rv_dm_bad_sba_tl_access | 81512542730555861810021847059523138637652577640872145076950915264895648549349 | 101 |
UVM_ERROR @ 1407390568 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @8631
|
|
| rv_dm_sba_tl_access | 82206225723696899431347259261214011317935522845394166450639443863848538516866 | 86 |
UVM_ERROR @ 2103344225 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5611
|
|
| rv_dm_autoincr_sba_tl_access | 21961992116195040171545856961815454773210958748615179018871877760227493549808 | 116 |
UVM_ERROR @ 2748693956 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @12051
|
|
| rv_dm_sba_tl_access | 65756264133886301026161093041149637091273271794360825713580051069502279510983 | 86 |
UVM_ERROR @ 660603222 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5479
|
|
| rv_dm_bad_sba_tl_access | 40822285915673591333278162736791877309793829011655898559043915409498811781260 | 89 |
UVM_ERROR @ 9478493564 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @12731
|
|
| rv_dm_autoincr_sba_tl_access | 94487443102824564544546355724868660412360492944045350768816756274884639444578 | 107 |
UVM_ERROR @ 25059047851 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @79205
|
|
| rv_dm_sba_tl_access | 46251218245818261974147596226302130579263243871830332806171558458860522555376 | 86 |
UVM_ERROR @ 3744082143 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5285
|
|
| rv_dm_bad_sba_tl_access | 104019180970992038479027336133049236410399978794238673727551798578182979894833 | 101 |
UVM_ERROR @ 1899161716 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @8907
|
|
| rv_dm_sba_tl_access | 49974594527141877896497556301541348446866931787109685980359461961371148143699 | 86 |
UVM_ERROR @ 1688246970 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5323
|
|
| rv_dm_sba_tl_access | 69983442849882199483517546876447897076072539278265594930399663375709889890745 | 86 |
UVM_ERROR @ 1953775764 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5367
|
|
| rv_dm_sba_tl_access | 789862085166159943583251435755827268653828611006094852077545467414615004255 | 86 |
UVM_ERROR @ 1171306137 ps: (rv_dm_scoreboard.sv:414) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5341
|
|
| Error-[CNST-CIF] Constraints inconsistency failure | ||||
| rv_dm_delayed_resp_sba_tl_access | 20596488534323633138913742186297021659720562540242688080881587575904692201040 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_bad_sba_tl_access | 58482034816446245416848056186074590005490882118067311872003449225940162272645 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 60160924604981636196830961745554461059379894232432231098984817747714993370331 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_bad_sba_tl_access | 74591076274260357817589462179027585020713972840607504974635793173736716997332 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 3165605474336750628377369962115301756374684968373284152895062665908245984911 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_autoincr_sba_tl_access | 34419650019354937241264392333799181219765285498911287440437142276288061253237 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 36459897148119838299144363966356706512594633445602304233119733927404250087138 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_bad_sba_tl_access | 43166210514221202704392920752050847806451548727012148892739584218145311663206 | 142 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 101341672601083316022378370255038646482419424597818375012350776777042478936743 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_autoincr_sba_tl_access | 8571370357193764142731107103511563586220599999049351509347671328822653985359 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 24496203538005640837449810275391743258393076374745541060802519135466606561721 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_bad_sba_tl_access | 19478353754478381299927438112281455712416222025937253699672829440939483408123 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 66424632851999778364712811929502609522595277372275408422096126506150029665330 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_bad_sba_tl_access | 108828040618982662734587211704731483684133549848376878377655401838542238349569 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 102067631287236965533118944071413116025041375208232747368920111020922503292128 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_bad_sba_tl_access | 83141053849177667680431926460274593544565275223901495727712993393035365903552 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 63787542267386259122666647517563611317614198707408686705597882611446032916994 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_bad_sba_tl_access | 5209646691657655832225640948346581334122344392404028712083127752802639208186 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_autoincr_sba_tl_access | 33239920254739125168200419281434804115122356270438499180806801322410575748789 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 11569414329854710767905211613240989877972416579275320598637040840468888445884 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 33908334187324253858876076963049233449196692014659003517907021149322761404003 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 85777758823355735891447799983621145982635467440923017774370924154142281714872 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_autoincr_sba_tl_access | 82149501416217249628571099074632759536877644296504743954194438776254693339816 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 8223120633337323589941319855681654912431762930461334945198689963615839869883 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_bad_sba_tl_access | 71525292014647742079025186910777371871442260731124820989775352270431770770618 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_autoincr_sba_tl_access | 73501087160492098977821534582766618483793009212142939557992552906468004953165 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 4141485580164546401891598454451300478943124825214806914984850034465252368556 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_bad_sba_tl_access | 108711446640833233410353240924982129958026640025772394891579549520938220375448 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 31190681165484861336338509011817644778019359002857521170211502882799549280864 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 66191942613827819760948495477072206639759361751371643377378454488672853910594 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 101734330313453175563883680679807053155891753631132175825834604283739943644589 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_bad_sba_tl_access | 88968256143571234712892163639475384335384985416604414950182843501551981700675 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_autoincr_sba_tl_access | 113640515696782121484304537007588819456559516219662627075903972274822748079109 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 10793183490564604867597526042069447358246543012819629160350456193954887211937 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_bad_sba_tl_access | 108168840814183908470238149596332357819390360217015657279274872375142415741532 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_autoincr_sba_tl_access | 24673796461746415249258965083188081131665374145414933517176861866881087160609 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_delayed_resp_sba_tl_access | 12076431211945442496104465774235030159721922481355031890650988824184346722170 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_bad_sba_tl_access | 98738467852802464989868903275784161036360735222612700294455050324308142652523 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| rv_dm_autoincr_sba_tl_access | 48154587395658256015505895083711050697422762057988766849652432853690659287874 | 133 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*]) | ||||
| rv_dm_mem_tl_access_resuming | 16459320553135711347947807690901450709821548256744905118304791067785505188953 | 77 |
UVM_ERROR @ 195873530 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 195873530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_mem_tl_access_resuming | 17641435090397686892379465103290188332289462894677133213544143682173272925670 | 77 |
UVM_ERROR @ 410793134 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 410793134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 88572754780337799846131573879546952672953051734229847684729614098218335577275 | 79 |
UVM_ERROR @ 488544781 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 488544781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 83587085064061462843541967506547148716747781599816743160799796901729473466903 | 78 |
UVM_ERROR @ 192416979 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 192416979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all_with_rand_reset | 18289083119693694757094046231792342059396994248458401678239056935641647748899 | 86 |
UVM_ERROR @ 150372196 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 150372196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all_with_rand_reset | 17135496805787771257947616532138941422560361725763664105722460915797455591525 | 80 |
UVM_ERROR @ 144991743 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 144991743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 29613845743038759506499332872054887275133393386271594161142070241022933568119 | 78 |
UVM_ERROR @ 364938308 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 364938308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 61836615092189320867476490373959730992923568727861641864874333927446889078866 | 80 |
UVM_ERROR @ 377908439 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 377908439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 31414689339297269478388456190414011481008210188698200951788014573149862644250 | 82 |
UVM_ERROR @ 1250551502 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1250551502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 101300260086305394706833251950347821743273934826382418317940594814465445627332 | 80 |
UVM_ERROR @ 1429496624 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1429496624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 49155094299364385091491119105260943627589137187638609401915184680541059505496 | 80 |
UVM_ERROR @ 313614137 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 313614137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 111855552653069146268378849840205163064510913936663576922694944366208745004205 | 109 |
UVM_ERROR @ 4833702563 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4833702563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 2574016494871069697076886066080903348186478809992425703094871270621070457099 | 81 |
UVM_ERROR @ 1553526389 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1553526389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 70680539528746031421875103428345885130383605323476071107029049326688809558806 | 78 |
UVM_ERROR @ 170423366 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 170423366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*]) | ||||
| rv_dm_hart_unavail | 61477437108072182370142398381250227924443107974860863368987106204700991213711 | 77 |
UVM_ERROR @ 67469899 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 67469899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all_with_rand_reset | 73919907098331101739131667164341880346442132027564377504397760068125396751035 | 92 |
UVM_ERROR @ 699884995 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 699884995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_hart_unavail | 66631723491798841627993991498475325250373332435533585302582204514052611019500 | 77 |
UVM_ERROR @ 73165974 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 73165974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_hart_unavail | 35998898582884296573968527901616934925017507781923662847587240781739852250154 | 77 |
UVM_ERROR @ 190695604 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 190695604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all_with_rand_reset | 82018743822014603321954166955896516256556154837337579097335536227574519866109 | 108 |
UVM_ERROR @ 2832040536 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2832040536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_hart_unavail | 105238228145346758788759225684356602422513286352240949353322391634064444793804 | 77 |
UVM_ERROR @ 43122134 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 43122134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 46980511850432685434233831975008396979700478754169914024651690940552643204600 | 80 |
UVM_ERROR @ 1419507662 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1419507662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all_with_rand_reset | 49836556671892538246693344805711803768485712780699298383664084396131923921466 | 88 |
UVM_ERROR @ 535532615 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 535532615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_hart_unavail | 12526973643950093154375402387161052443442856629499610567083100157194864809515 | 77 |
UVM_ERROR @ 270193687 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 270193687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 28796226907404180085274853742763604774745713775706518114314916761354240636719 | 79 |
UVM_ERROR @ 2240626404 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2240626404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all_with_rand_reset | 5017569199342006274089337724766928996925959526135722080107442375133678817067 | 94 |
UVM_ERROR @ 982892820 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 982892820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 22792382867089210755319402651403718800511523470631662731602413868223610322630 | 83 |
UVM_ERROR @ 6172681841 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6172681841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 101719993605308616851295646801261870062214966013414476031385802894457177758820 | 91 |
UVM_ERROR @ 2769622799 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2769622799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 41889471640991160317804860752571603841721995294561333923051479835505961121935 | 80 |
UVM_ERROR @ 390910132 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 390910132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 15466527551925944780400811530945052537299884949978098509609390015395545595117 | 79 |
UVM_ERROR @ 554487907 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 554487907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 47000364140103474801708642607532453113582720545418444014386082699069891348663 | 78 |
UVM_ERROR @ 176430664 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 176430664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 97784776899700832624237501257890133018427593315684113054698614831234278488895 | 80 |
UVM_ERROR @ 1027222586 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1027222586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 114370140719506209807787421549854237074317478493076339266447763676335590232851 | 81 |
UVM_ERROR @ 2784852317 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2784852317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 83659542711858206632132210070771203019843627265071413610401651775405706404195 | 78 |
UVM_ERROR @ 253252187 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 253252187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 110082079941277323375721224490196266461943059573851839377793512216973010665806 | 79 |
UVM_ERROR @ 578219143 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 578219143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 41416600516252815713331653359203356837669008221210447911774126760424461952330 | 78 |
UVM_ERROR @ 284417689 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 284417689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 109618848703050336651533346836098072486895377970653926916367051608783604333396 | 81 |
UVM_ERROR @ 4058372383 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4058372383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) | ||||
| rv_dm_jtag_dmi_debug_disabled | 43944271816944334506142510504027488915894674804898495499535999189638761607848 | 77 |
UVM_ERROR @ 151347927 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (928437804 [0x3756d62c] vs 0 [0x0])
UVM_INFO @ 151347927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_jtag_dmi_debug_disabled | 77037345306988739577738914822256053668625375549730785409847598852478942006125 | 77 |
UVM_ERROR @ 81035378 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2156168482 [0x80848522] vs 0 [0x0])
UVM_INFO @ 81035378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 50549747591253425684528537005432032730153957319202525333373705137089504213487 | 81 |
UVM_ERROR @ 1905369009 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2716233794 [0xa1e67042] vs 0 [0x0])
UVM_INFO @ 1905369009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all_with_rand_reset | 46103400803987562155307011962630652612445560929467027303043561169809818810838 | 114 |
UVM_ERROR @ 913735002 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1580578798 [0x5e35b7ee] vs 0 [0x0])
UVM_INFO @ 913735002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 78843593213319931943094756332468809136187685556092655989473608525240165752311 | 83 |
UVM_ERROR @ 6718643777 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2486098517 [0x942eda55] vs 0 [0x0])
UVM_INFO @ 6718643777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 2007810895579947640639019349607344814732610159110072613652790604246092645565 | 78 |
UVM_ERROR @ 438098600 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4225734770 [0xfbdf9872] vs 0 [0x0])
UVM_INFO @ 438098600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 8073445198809186865057653477330488024063078692754022264630241774067446041587 | 83 |
UVM_ERROR @ 2810934248 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2433265591 [0x9108afb7] vs 0 [0x0])
UVM_INFO @ 2810934248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 54882716741223966806485067768708365984635014401069236519609897477047566811796 | 84 |
UVM_ERROR @ 4151880987 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3664487263 [0xda6ba35f] vs 0 [0x0])
UVM_INFO @ 4151880987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 9605587643086361274573182821976806776519336568845992281750625739631560927299 | 79 |
UVM_ERROR @ 1149468481 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2341065654 [0x8b89d3b6] vs 0 [0x0])
UVM_INFO @ 1149468481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 14195292208708022511718831385231581827806119107412189576702602791951345890489 | 79 |
UVM_ERROR @ 1228561161 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (735030761 [0x2bcfade9] vs 0 [0x0])
UVM_INFO @ 1228561161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 88088162078819476811266466325167945589750646383272613334994237004543426531488 | 78 |
UVM_ERROR @ 101559082 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2529824901 [0x96ca1085] vs 0 [0x0])
UVM_INFO @ 101559082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 110450082133647861306177629068006528071000791566413857417570808099655448564762 | 78 |
UVM_ERROR @ 455647482 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1954115404 [0x74796f4c] vs 0 [0x0])
UVM_INFO @ 455647482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 954378731078307067606523629105107109080319849479831573966490964740193057215 | 79 |
UVM_ERROR @ 614469510 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1918839048 [0x725f2908] vs 0 [0x0])
UVM_INFO @ 614469510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 83360322883774170582633515969419242092967492931369186054522555962037076283311 | 78 |
UVM_ERROR @ 91996753 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3251149939 [0xc1c89c73] vs 0 [0x0])
UVM_INFO @ 91996753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output) | ||||
| rv_dm_debug_disabled | 37539578026710397690513375260238422304695866674995183172659485756230725895022 | 80 |
UVM_ERROR @ 21483679 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
UVM_INFO @ 21483679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | ||||
| rv_dm_scanmode | 109469131790096691835745780555754289556667771613076356773199332432258135570418 | 77 |
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 56625176550102878954254077959147442108201339296206841985369497263004242618313 | 81 |
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 2028852727798811220165024307514134127522863985239964760835409302188510191880 | 78 |
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 37703566570815132671265961001833635732434061069886640976485897041735472983301 | 78 |
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 4319975326002826103176044961848980441384867367214413383000381852082657437112 | 82 |
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done) | ||||
| rv_dm_stress_all_with_rand_reset | 61349074389057758089354196801557794304922683556767820415131791901279675137012 | 92 |
UVM_FATAL @ 3994197940 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 3994197940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all_with_rand_reset | 9554907762411936310524009950797352780350799916781846335490386067005219127368 | 85 |
UVM_FATAL @ 624391141 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 624391141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all_with_rand_reset | 90908634373637358743913076927682562151572105944144953954323063146270776598415 | 88 |
UVM_FATAL @ 231419075 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 231419075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*]) | ||||
| rv_dm_buffered_enable | 6362951119882507754921971993679553786211961658791738004857322255201657925072 | 82 |
UVM_ERROR @ 303553928 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1])
UVM_INFO @ 303553928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | ||||
| rv_dm_stress_all | 100736200092946341362386521761480428574813755257586650133353449660594203054759 | None |
Job timed out after 180 minutes
|
|
| rv_dm_stress_all | 3029692689301317473306571510578753977639358933460828877281200667256055986977 | None |
Job timed out after 180 minutes
|
|
| rv_dm_stress_all | 44286305095277437169490070890417319532192797807651375619842130022379613217608 | None |
Job timed out after 180 minutes
|
|
| rv_dm_stress_all | 40372882871909607711860238688174581093492850521784738614672304315983514338134 | None |
Job timed out after 180 minutes
|
|
| rv_dm_stress_all | 112986172535160938113561916381048017416007043851283749683828110782643704223601 | None |
Job timed out after 180 minutes
|
|
| rv_dm_stress_all | 45437473189902019457226864752593375923435508427355848196074462218248171827613 | None |
Job timed out after 180 minutes
|
|
| rv_dm_stress_all | 39657789608998355889101907915563195529258012802010076041679773517102424018196 | None |
Job timed out after 180 minutes
|
|
| rv_dm_stress_all | 6531219069655044109193962131854109590397129634870632785882892536511194971531 | None |
Job timed out after 180 minutes
|
|
| rv_dm_stress_all | 96588030632412483788488135486960273676876541409180567709697137268169323564339 | None |
Job timed out after 180 minutes
|
|