| V1 |
|
100.00% |
| V2 |
|
92.50% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.700s | 1126.209us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.800s | 14.699us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.950s | 38.476us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 3.230s | 1925.261us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 1.150s | 38.624us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.470s | 33.304us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.950s | 38.476us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.150s | 38.624us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 2 | 20 | 10.00 | |||
| rv_timer_random_reset | 10.980s | 185748.505us | 2 | 20 | 10.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 2.890s | 1719.224us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 434.210s | 563938.674us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 434.210s | 563938.674us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 7.550s | 4392.878us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.920s | 15.356us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.900s | 21.467us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 3.000s | 368.771us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 3.000s | 368.771us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.800s | 14.699us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.950s | 38.476us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.150s | 38.624us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.100s | 55.408us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.800s | 14.699us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.950s | 38.476us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.150s | 38.624us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.100s | 55.408us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 1.200s | 93.988us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.470s | 307.237us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.470s | 307.237us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 2 | 10 | 20.00 | |||
| rv_timer_min | 1.810s | 113.413us | 2 | 10 | 20.00 | |
| max_value | 1 | 10 | 10.00 | |||
| rv_timer_max | 1.230s | 85.996us | 1 | 10 | 10.00 | |
| stress_all_with_rand_reset | 17 | 20 | 85.00 | |||
| rv_timer_stress_all_with_rand_reset | 73.510s | 34385.636us | 17 | 20 | 85.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_min | 1531938730084181805151335603954261366529534426468790421446707160049845738055 | 75 |
UVM_FATAL @ 103790599 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x43bd04) == 0x1
UVM_INFO @ 103790599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 66088876939598809977067117867855109564232133599526403566291168805728576349517 | 75 |
UVM_FATAL @ 1627080187 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4f30304) == 0x1
UVM_INFO @ 1627080187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 46508063631510692512867641707238230551960662204764079559418475994488416392762 | 78 |
UVM_FATAL @ 81136461 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x36430704) == 0x1
UVM_INFO @ 81136461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 53787029561825218110225870272695763949833874224869264524404519462550128101684 | 75 |
UVM_FATAL @ 56928563 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd5f3b704) == 0x1
UVM_INFO @ 56928563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 20841808225427996613607816720598791881094369039266434264727324273311837750938 | 75 |
UVM_FATAL @ 60716079 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x84ba0b04) == 0x1
UVM_INFO @ 60716079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 70874769870309571033139809945211972775933275121324518008131992743129880616109 | 75 |
UVM_FATAL @ 1123471923 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3c434104) == 0x1
UVM_INFO @ 1123471923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 18853312706283995761754943213690242108315494012392967978427967177594870056867 | 76 |
UVM_FATAL @ 118282340 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa1aa9304) == 0x1
UVM_INFO @ 118282340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 53354629669892844231639251267497935762224779242109896005196828532602033396619 | 75 |
UVM_FATAL @ 185748504955 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe92cd104) == 0x1
UVM_INFO @ 185748504955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 111197475208805252845215742558072419009332045320130251462377181017580019841846 | 76 |
UVM_FATAL @ 4210440247 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6ddb1904) == 0x1
UVM_INFO @ 4210440247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 23430371535736967345125000476737333024466109059073304612658022836836581798813 | 76 |
UVM_FATAL @ 888462729 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x93d51d04) == 0x1
UVM_INFO @ 888462729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 103581599504052256344683946707430453166808669460265722974251778707394038596383 | 75 |
UVM_FATAL @ 72891434 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x299f9d04) == 0x1
UVM_INFO @ 72891434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 86302008188271049413798482365594634499277226864888439380551587169365060466107 | 76 |
UVM_FATAL @ 220354104 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5f26c504) == 0x1
UVM_INFO @ 220354104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 98714983281591471409436110014109876330772721261064596456506809007666012904205 | 76 |
UVM_FATAL @ 660092365 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xfe5a7904) == 0x1
UVM_INFO @ 660092365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 35284875901480675975315740306016625460567476450602337404490053683744385043776 | 75 |
UVM_FATAL @ 113412679 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x23cb7704) == 0x1
UVM_INFO @ 113412679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 8874881551844817217986458377082273663016633567239922496853734063571973644409 | 75 |
UVM_FATAL @ 182827420 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xca639f04) == 0x1
UVM_INFO @ 182827420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 71176620105245499993957200777323968988688447793837013734366471178944519798592 | 79 |
UVM_FATAL @ 128181020 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf79d5704) == 0x1
UVM_INFO @ 128181020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 90191294117541869171577042682309685496204618086457927940801702151480634155546 | 75 |
UVM_FATAL @ 1255600683 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xad87504) == 0x1
UVM_INFO @ 1255600683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 95394193315346076629373545041840431323242890267247849544647042251574113503330 | 75 |
UVM_FATAL @ 227710487 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x24e93504) == 0x1
UVM_INFO @ 227710487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 55874681695620199015082780243056827851779541006975205322430944476557580359450 | 75 |
UVM_FATAL @ 293459310 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x79f79d04) == 0x1
UVM_INFO @ 293459310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 53416696354016275283059196903639515996866693327396221191217775553445904775687 | 75 |
UVM_FATAL @ 216261831 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6e6ab704) == 0x1
UVM_INFO @ 216261831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 21414769144127113946481287567054262918948557573591966660694562549354524821507 | 75 |
UVM_FATAL @ 1689325423 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x62ec0304) == 0x1
UVM_INFO @ 1689325423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 42747443924967558079676583543662599604403006674169528070096396901588254790621 | 75 |
UVM_FATAL @ 189426795 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x84418d04) == 0x1
UVM_INFO @ 189426795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 72843626935779339210956420216900178110679173236729576535597827979299991270696 | 75 |
UVM_FATAL @ 2248480065 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x9463a104) == 0x1
UVM_INFO @ 2248480065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 80191863999738337251972874887754619497023511360349356054030335348673782905309 | 75 |
UVM_FATAL @ 92036443 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x28504904) == 0x1
UVM_INFO @ 92036443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 5822641457689554068170803460282726125615149303177795830755087805795157184776 | 75 |
UVM_FATAL @ 180028907 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe2ff0f04) == 0x1
UVM_INFO @ 180028907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 74234324902153156731541143598464324133844616999787031908077677152779999308883 | 76 |
UVM_FATAL @ 143403933 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x46f8b04) == 0x1
UVM_INFO @ 143403933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 40343727905362726838896300273609075371598012677330494342794770351449596819489 | 75 |
UVM_ERROR @ 324429313 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 324429313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 90615364765334789291953457707774828811196061476344281571290460289571289108728 | 75 |
UVM_ERROR @ 44310363 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 44310363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 55459500102758722877122386061625556119142228023054228765378628105891424278655 | 75 |
UVM_ERROR @ 44655896 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 44655896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 51920571103608070137226101659679421088914803511438298394031455474346062909369 | 75 |
UVM_ERROR @ 42574865 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 42574865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 40018083828937775412624752298760113471457977974886700438596300757250930060033 | 75 |
UVM_ERROR @ 365728797 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 365728797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 105781891057044126684413416457510874853109890886573331850326557159861050580211 | 75 |
UVM_ERROR @ 44415564 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 44415564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 15900657103604501010916657938937121243986459076127303810638535067870031765801 | 75 |
UVM_ERROR @ 85995807 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 85995807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 2871248094162032200925480236643111602895478178752129829195429859760498250370 | 75 |
UVM_ERROR @ 88196198 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 88196198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 68237801841033835929794469231862557677723151803778413848399437164061138849453 | 77 |
UVM_ERROR @ 264573838 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 264573838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 63684239883019475678562296940551998821099549161553983172725124853541494931775 | 231 |
UVM_FATAL @ 20385474982 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 20385474982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 9130237088014923038435911749297549524484576273995715953629410443274554841116 | 79 |
UVM_FATAL @ 4404286 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 4404286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 28551180354403299687582769862847825944896835565315693052957836199331263117726 | 323 |
UVM_ERROR @ 20344237731 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 20344237731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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