Simulation Results: sram_ctrl/main

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.51 %
  • code
  • 96.88 %
  • assert
  • 96.46 %
  • func
  • 96.20 %
  • block
  • 96.22 %
  • line
  • 96.96 %
  • branch
  • 94.49 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 6.000s 369.505us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 14.652us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 22.968us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 4.000s 346.598us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 18.453us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 6.000s 4981.745us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 22.968us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 18.453us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 212.000s 21885.406us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 113.000s 2516.734us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 69.000s 7877.416us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 231.000s 11155.194us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 155.000s 9537.511us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 64.000s 14306.783us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 67.000s 86089.772us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 39.000s 7269.900us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 5.000s 712.547us 5 5 100.00
sram_ctrl_partial_access_b2b 233.000s 14034.899us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 8.000s 2887.177us 5 5 100.00
sram_ctrl_throughput_w_partial_write 7.000s 716.903us 5 5 100.00
sram_ctrl_throughput_w_readback 9.000s 1372.394us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 20.000s 874.179us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 4.000s 365.318us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 443.000s 127661.078us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 168.708us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 527.777us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 527.777us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 14.652us 5 5 100.00
sram_ctrl_csr_rw 2.000s 22.968us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 18.453us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 43.934us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 14.652us 5 5 100.00
sram_ctrl_csr_rw 2.000s 22.968us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 18.453us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 43.934us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 56.000s 117102.638us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 5.000s 439.792us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 287.831us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 439.792us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 287.831us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 20.000s 874.179us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 20.000s 874.179us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 22.968us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 39.000s 7269.900us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 39.000s 7269.900us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 39.000s 7269.900us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 67.000s 86089.772us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 7.000s 1422.181us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 56.000s 117102.638us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 7.000s 1341.881us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 6.000s 369.505us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 6.000s 369.505us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 39.000s 7269.900us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 439.792us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 67.000s 86089.772us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 439.792us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 439.792us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 6.000s 369.505us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 439.792us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 29.000s 1520.166us 5 5 100.00