Simulation Results: sram_ctrl/ret

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.24 %
  • code
  • 83.49 %
  • assert
  • 96.43 %
  • func
  • 96.80 %
  • block
  • 94.01 %
  • line
  • 95.19 %
  • branch
  • 89.83 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
92.86%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 2.000s 84.343us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 29.000s 28.967us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 29.000s 22.597us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 30.000s 183.050us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 29.000s 25.198us 5 5 100.00
csr_mem_rw_with_rand_reset 15 20 75.00
sram_ctrl_csr_mem_rw_with_rand_reset 29.000s 47.816us 15 20 75.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 29.000s 22.597us 20 20 100.00
sram_ctrl_csr_aliasing 29.000s 25.198us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 12.000s 1850.855us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 6.000s 360.198us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 10.000s 979.809us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 183.000s 12604.486us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 8.000s 1261.502us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 22.000s 3132.273us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 7.000s 2213.467us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 17.000s 1807.439us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 3.000s 275.466us 5 5 100.00
sram_ctrl_partial_access_b2b 368.000s 19248.591us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 2.000s 136.689us 5 5 100.00
sram_ctrl_throughput_w_partial_write 2.000s 138.288us 5 5 100.00
sram_ctrl_throughput_w_readback 2.000s 34.526us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 10.000s 841.425us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 77.831us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 45.000s 3668.654us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 29.821us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 30.000s 131.782us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 30.000s 131.782us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 29.000s 28.967us 5 5 100.00
sram_ctrl_csr_rw 29.000s 22.597us 20 20 100.00
sram_ctrl_csr_aliasing 29.000s 25.198us 5 5 100.00
sram_ctrl_same_csr_outstanding 29.000s 13.986us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 29.000s 28.967us 5 5 100.00
sram_ctrl_csr_rw 29.000s 22.597us 20 20 100.00
sram_ctrl_csr_aliasing 29.000s 25.198us 5 5 100.00
sram_ctrl_same_csr_outstanding 29.000s 13.986us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 31.000s 2231.531us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_tl_intg_err 30.000s 1037.119us 20 20 100.00
sram_ctrl_sec_cm 5.000s 1153.472us 5 5 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 1153.472us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 30.000s 1037.119us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 10.000s 841.425us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 10.000s 841.425us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 29.000s 22.597us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 17.000s 1807.439us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 17.000s 1807.439us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 17.000s 1807.439us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 7.000s 2213.467us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 487.343us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 31.000s 2231.531us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 2.000s 40.737us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 2.000s 84.343us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 2.000s 84.343us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 17.000s 1807.439us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 1153.472us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 7.000s 2213.467us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 1153.472us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1153.472us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 2.000s 84.343us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1153.472us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 36.000s 1037.783us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 460850938484105116293439745332779949342897450995224418891817693479867510854 88
UVM_ERROR @ 99262754 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
UVM_INFO @ 99262754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 59482162719439185800970534861212313542803779625507703383509004595657549447347 88
UVM_ERROR @ 24497326 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 24497326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_csr_mem_rw_with_rand_reset 79415982525233301603698196757692663776242193439259476578312070941336949585484 88
UVM_ERROR @ 98008995 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 98008995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 103754726778793361910975748871377310175728480668521028958992355969266703024228 88
UVM_ERROR @ 90687716 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 90687716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_csr_mem_rw_with_rand_reset 46471439497226385172111335525002847297199856540241531747528606487679373794329 88
UVM_ERROR @ 94627174 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 94627174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---