Simulation Results: ac_range_check

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
98.95%
V2
96.68%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 20 20 100.00
ac_range_check_smoke 51.000s 7438.884us 20 20 100.00
ac_range_check_smoke_racl 19 20 95.00
ac_range_check_smoke_racl 65.000s 2704.726us 19 20 95.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 12.000s 320.833us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 3.000s 292.931us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 48.000s 1640.991us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 47.000s 5497.734us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 10.000s 28.660us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 3.000s 292.931us 20 20 100.00
ac_range_check_csr_aliasing 47.000s 5497.734us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 60.135us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 62.000s 8437.899us 1 1 100.00
stress_all 42 50 84.00
ac_range_check_stress_all 286.000s 11372.231us 42 50 84.00
alert_test 50 50 100.00
ac_range_check_alert_test 27.000s 50.391us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 2.000s 115.111us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 7.000s 168.237us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 7.000s 168.237us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 12.000s 320.833us 5 5 100.00
ac_range_check_csr_rw 3.000s 292.931us 20 20 100.00
ac_range_check_csr_aliasing 47.000s 5497.734us 5 5 100.00
ac_range_check_same_csr_outstanding 7.000s 1287.294us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 12.000s 320.833us 5 5 100.00
ac_range_check_csr_rw 3.000s 292.931us 20 20 100.00
ac_range_check_csr_aliasing 47.000s 5497.734us 5 5 100.00
ac_range_check_same_csr_outstanding 7.000s 1287.294us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 1261.861us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 1261.861us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 1261.861us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 1261.861us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 112.000s 4099.627us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 2.000s 41.325us 5 5 100.00
ac_range_check_tl_intg_err 13.000s 832.787us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 417.000s 7097.156us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 50.000s 1548.648us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 8 test runs
ac_range_check_stress_all 49549968265235687276655686883948668732514256513354662431278319832859885917311 29104
UVM_INFO @ 6148100880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 72380601453588708121268156322985277274477503201498930116210387593312428451760 3954
UVM_INFO @ 19344541886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 5152433479798843534324639043890471031434970423612026115589897636132832974855 13005
UVM_INFO @ 6163171612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 49745229934076499637953828232182163234551465881880415118683510334936096144664 12917
UVM_INFO @ 5912871088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 26877646930026784108936699295116465972532981092663998604788745536384714944133 13617
UVM_INFO @ 79280575229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 87601513164905773093973441880126583418793685763185653655722523547159387622230 4847
UVM_INFO @ 17514458584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 48115944866720598935575092893106430439246457490191033485971112715453368219908 4193
UVM_INFO @ 1339065214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 42753815317254211328083716967399170621870714400638894570469979486128370613080 4229
UVM_INFO @ 5567250182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_scoreboard.sv:166) [scoreboard] Unable to get any item from tl_unfilt_d_chan_fifo. 1 test run
ac_range_check_stress_all 60069085084451630361864673446271376882064919051790183461755721100669441572205 20512
UVM_INFO @ 100422629864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---